Research On Embedded IP Cores Testing By Reusing NoC Structure

The main test mode of embedded IP cores based on NoC is reusing the inherent channels totransmit testing data. But the design and optimization of traditional framework of NoC are based onthe normal function mode, which puts forward the severe challenge for how to reuse the channels ofNoC to test the embedded cores efficiently and reliably. Based on the synthetical analysis ofcommunication characteristic of NoC and IEEE1500standard, the subject of study is to seek anefficient TAM of embedded IP cores by reusing the communication structure of NoC. As a result, theIP cores of2D-Mesh topology can be tested by this way effectively.Based on studying the communication characteristic of NoC in detail, this paper introduces themulticast of internet to the router’s design of NoC. Through the design of the multicast for NoC, theparallel transmission of a large number of test data for multi-node can be realized. By mean of thisway, the access of the embedded cores under test mode is accomplished. Because of the fact that thestructures of IP cores are different, it brings more difficulties to the reuse of the test circuits. Throughdesigning the IEEE1500wrapper for different embedded IP cores, all the cores become homogeneousfrom the point of test integration and can be tested by the same way conveniently and effectively.After designing the TAM and various wrapper for the IP cores of NoC, the cores embedded in theNoC are tested by using the test platform of4×4Mesh topology. With the Synthetic analysis of thefactors such as the number of ports, the test power dissipation, the test time and so on, the paperfinally obtains the best test solution of embedded IP cores of4×4Mesh topology is multicast modewith eight destinations.The RTL model of NoC and IEEE1500wrapper are realized by using Verilog HDL. Weaccomplish the function simulation of modules and the test simulation of system on VCS of EDAplatform of Synopsys. The simulation results demonstrate that the design satisfies the request. Finally,we synthesize the algorithm on DC of Synopsys to analyze area and power cost. The study of testmechanism of embedded IP cores of NoC provides a valuable reference to the test of NoC system.