Design And Optimization Of Power Consumption And Noise In CIS Control System

Compared with CCD, CMOS Image Sensor has many advantages, for example, low cost, low power consumption, easy integration and flexible high-speed reading, etc. So in the areas of consumer digital, medical imaging, industrial monitoring, high definition broadcast and video communications, CMOS Image Sensors are gradually replacing the mainstream status of CCD Image Sensors. This paper mainly research on the controlling circuit system of high performance CMOS image sensor.The controlling circuit is the most important part of the CMOS Image Sensor system, including exposure control circuits, read-out control circuits, I2C bus control circuit, APB bus control circuit and the darkcurrent cancellation circuit modules.A Rolling Shutter timing control circuit of CMOS Image Sensor is implemented in this paper, using I2C and APB bus as the register control interface.In addition, the low power consump-tion design technology in the design of CMOS Image Sensor is studied, and clock gating is used to reduce the power consumption of standby state. By compensation of voltage, the reset level of all pixels are equal, the traditional CDS circuit is improved.In order to remove temporal row noise in CMOS image sensor, a new readout timing based on conventional correlated double sampling is proposed in this paper. The new readout timing is row correlated double sampling, operating two rows at the same time. Temporal row noise is sampled to the capacitor at the same time when sampling the image signal, and removed by the switch capacitor amplifier.The CMOS image sensor is completed and implemented based on dongbu 0.18μm CMOS technology. The chip size is 1/6 inch, pixel array is 640×480, and the pixel size is 2.8μm, dark current of pixel is 3mV/s, the dynamic range is 62dB. The test results show that the new timing control present in this paper can effectively eliminate the row noise, and the imge quality is significantly improved. The standby current is only 30μA, compared to traditional design methods, the power consumption of the chip is reduced by 60%.