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Research On Image Matching Algorithm And Its High Speed Parallel Implementation

Posted on:2011-12-01Degree:MasterType:Thesis
Country:ChinaCandidate:L H LuFull Text:PDF
GTID:2248330338996559Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
The image matching has been widely used in stereo vision, image mosaicing, image retrieval, photogrammetry and remote sensing, resource analysis, three-dimensional reconstruction and object recognition, and other fields, and it has been the focus of researchers. To meet the requirements for real-time, normalized cross correlation template matching, SIFT algorithm, and their high speed parallel implementation based on FPGA to improve the speed performance of the system are studied in this paper.For image matching based region, template matching based on normalized cross-correlation (NCC) measure is maily studied. To improve the location accuracy and speed performance, combined with the Sobel edge detection, a improved high-speed parallel architecture for real-time implementation of template matching with NCC, using field programmable gate array (FPGA) are proposed in this paper. In this architecture, several novel efficient approaches are proposed to reduce logic resource usage and computation time. A comparative study of the template matching before and after image edge detection has shown that image edge detection can sharpen the ridge of the NCC results. Function and timing simulation and practical experiment for automatic target recognition applied in infrared missile guidance system have shown that this architecture can effectively improve the speed performance of the practical system with little extra computation time. Furthermore, the hardware implementation based on FPGA can reduce the system size.For image matching based feature, SIFT and PCA-SIFT are mainly studied in detail. Simulation results based on the real images for a comparative study are given. To improve the speed performance, a high-speed parallel architecture for real-time implementation of SIFT algorithm is proposed. In this architecture, many strategies are proposed to to reduce logic resource usage including efficient parallism stategies, CORDIC algorithm and fixed point operation. Furthermore, NIOS II microprocessor is also used to provide more flexibility to implement PCA-SIFT algorithm through a simple software modification in NIOS II microprocessor.
Keywords/Search Tags:Image Matching, NCC, FPGA, SIFT, Parallel Architecture
PDF Full Text Request
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