Research On The Fast Matching Method For Remote Sensing Image Based On SoC Technology

The automatical interpreting technology of remote sensing image is an important research field, while image matching is the most critical key in it. In recent decades, the image matching technology is always an hot and difficult issue in Computer-vision research field. With the rapid development of sensor technology, the resolution of remote sensing images becomes much higher, meanwhile the size and information quantity are all larger and larger, so all of which have increased the difficulties, complexity, calculation amount for processing images. At present, the algorithms which have better matching effect can’t meet the real-time requirement for big images. In order to meet real-time requirement for processing image, many ways, such as Algorithm-design, Software and hardware cooperative implementation, etc, are needed by cross using. This thesis focuses on real-time image matching, researching the ways of real-time implementation for image matching, which has important theoretical significance and application value.Now, image matching algorithms can be mainly classified into two categories:matching algorithm based on gray and ones based on feature. Among them, for the advantages of better image processing effect and algorithm robustness, matching algorithms based on feature are widely used in non-real-time processing field. For the reason of more complex calculation, this kind of algorithms can’t meet real-time requirement. With the rapid development of chip-technology(especially the programmable chips), and SoC technology, it is feasible to implement image matching algorithm according to chip-design and parallel processing technology. At present, some FPGA chips based on the 20-Nano CMOS technology, have contained hundred millions of transistors, and whose frequency has approached GHz. So, for the outstanding advantages of high integration, low power consumption, and small size, the way based on SoC FPGA will be main stream in the embedded filed of image processing in the future. In this thesis, image matching algorithm is implemented by the way based on SoC FPGA.This thesis devotes to the theoretical and technical research of fast image matching method, and focus on the practical needs of embedded application for remote sensing form the two points of view of algorithm and chip-system design. The main works and achievements are as follows:1) A new algorithm which is applied to fast match via mixed scales searching for big images is proposed. It may decrease matching calculation amout greatly, if the two ways of exponential and linear scale transform are combined for image rough matching and precise matching. When exponential way is used, the low frequency sub-image after wavelet transform can be used to get a rough place, which is set as a starting point of searching, and then get the partial, precise location in original image via the linear way. In the two matching ways, the algorithms based on features and linear sacle transform, such as SIFT algorithm, can be applied. This kind of algorithms possesses high matching probability and precision, while high complexity, so it plays important role in the process of locating the staring point if the 2-d wavelet transform and low frequency sub-image are applied. The low frequency sub-image after wavelet transform maintains principal features of original image, the main purpose of initial search is to get a rough place, so 2-d wavelet transform cut down search range greatly, for example, if wavelet transform is applied twice, the obtained low frequency sub-image is one sixteenth of original, obviously it is simpler to search features on this sub-one. Now, traditional SIFT algorithm employs linear scale splace, whose change direction is linear, in the field of real-time, such transformation speed is too slow and complex. In proposed algorithm of this thesis, the lifting scheme wavelet transform which suitable for parallel implementation via hardware is applied, it is convenient for the whole algorithm design. It shows that, compared with traditional SIFT algorithm, the calculation amount of new proposed is one-third at least via theoretical analysis and simulation. Moreover, the parts, such as wavelet, feature extraction and matching, may handle separately, it is suitable for parallel circuit designing via hardware.2) The design method and constraint condition of wavelet filter used to cut down image space when roughly match are studied and proposed. Low frequency and high frequency informations of images describe globle characteristics and local features independently, and rough matching focuses on globle characteristics. It needs to design the decomposition filter if want to separate frequency informations of image and roughly match, while the filters is designed by the way of lifting scheme wavelet transform. The process of lifting scheme wavelet transform, different with SIFT algorithm, is another scale transform, whose way of scale change is exponential. The scale-set based on wavelet transform should be a sparse subset of SIFT. In a same scale, the low frequency response based on wavelet filter should be almost the same, only in this way can it maintain the low frequency of describing image features. The similarity measurement of image matching algorithms is based on image features(scilicet descriptors), in this thesis, based on characteristics of various wavelet filters, the effects of wavelet transform to descriptor is studied, and then obtain a constraint condition of designing wavelet filters in big image fast matching algorithm.3) Focus on traditional SIFT algorithm, a new design via hardware circuit based on integrated circuit technology is proposed. The traditional SIFT algorithm is implemented on software platform, applied floating point computation, curve fitting, serial iterative, linear interpolation, etc, and then the whole process is serial. If want to transplant SIFT algorithm on hardware, it should adopt parallel processing to redesign all modules of SIFT. In this thesis, technologies, such as parallel architecture, fixed-point calculation, multiplexing storage, distributed management, etc, are applied to design integrated circuit. For the module of main direction judgement, in this thesis, a new way of neighbourhood information extraction for pole distribution points is proposed, compared with traditional SIFT, it operates via address search and data statistic only, and don’t need multiplication and extra storge space. In order to reduce the complexity of similarity algorithm, binarization measurement method for image features is proposed, different with euclidean distance, binarization descriptors apply hamming distance to measure similarity, and this way is suitable for parallel circuit design. Simulation shows that, improved SIFT algorithm via integrated circuit, not only maintain matching precision, but also accelerate algorithm speed.4) A new fast matching method via image texture to pre-judge features distribution for remote sensing images is proposed. The maching time is proportional to the pixel amount of image, for big images, whose features points are evenly distributed, if their statistic characteristics of features points distribution can be known in advance, most useless calculations may be avoided, and then speeds up. Thcrs are great difference for statistic characteristic of remote sensing image features contained in different landform, it can be used to pre-judge the matching ways directly via image texture features if these characteristic have been known. For some remote sensing images, according to roughly matching, and then get a precise matching location. While for another images, it must apply first rough matching, then precise matching method to get a get a precise matching location. For the matching way via integrated circuit. The pre-judge module can be seen as a front end circuit, and apply pipeline to connect with matching module. This way may reduce calculations, and speed up matching for remote sensing images.5) The design method for proposed image matching algorithm via SoC FPGA chips is studied. The main modules of algorithm are redesigned and implemented in SoC FPGA chip of Xilinx Zynq 7000 series. In the chips of Xilinx Zynq 7000 series, there are PL(FPGA array) and PS(ARM contained Cortex-M9 dual-core processor), which are managed and scheduled via embedded Linux operating system. The time-consuming modules, such as wavelet transform, texture pre-judge and SIFT algorithm, are implemented in PL, and the module to match descriptors is in PS. Modules different in PL and PS communicate via Xilinx AXI bus. In system, the imported and exported data are valid via Linux to open I/O IP-core, gigabit ethernet is appied to exchange data with outside, meanwhile, some modules with small calculations are implemented in PS also. For software design in chip, it apples multithread technology, which dynamically assign tasks to that two CPU core, and then speeds up further. Now, to generate descriptors for a 1600 X 1050 color remote sensing image, it takes 25 second via software, but 6 millisecond via method proposed in this thesis. According to test on more than 200 sets of images, it is found that hardware method is 3 orders faster than software. If the SoC FPGA chips which possess more hardware resources are applied, normally it will take 10 millisecond to match, and then may meet real-time in most situations.