FPGA Design And Implementation Of Data Capture System Based On PCI-E Interface

Plenty of information is provided with the rapid development of network technology of information age. As the data carried by the network increases, the size-growing of the network rises as well, thus, effective collection of the real-time high-speed data stream is of high importance in the area of network monitoring and security. The system of data acquisition card acquires real-time data stream which become high-flow, high-speed data stream after processing in high-speed network, Afterwards those data are transmitted to host server. With the development of the high-speed IO bus technology, implementation of this high-performance data acquisition system becomes feasible.PCI Express bus is the third generation high-performance IO bus which was developed on the basis of traditional bus, featuring high-speed, high reliability, low cost and expandability. Both of the large severs and micro-computer systems demonstrate the well compatibility with the PCI Express. Among all the current hardware system via IO bus for interaction, PCI Express also becomes the top choice of majority systems which are aiming the high-speed transmission.Based on the research and understanding of the high-speed data acquisition system and its related technology, combined with the analysis of the PCI Express IO architecture and key techniques, this thesis presents a new method for high-speed data acquisition system based on PCI Express bus to achieve the functional and performance requirements. The system consists of hardware logical design and software driver, this thesis mainly emphasis and elaborate the design and implementation of the system from the perspective of hardware logics. The thoughts of modular is used in system hardware logical design, the entire system is divided into three parts: Access of Gigabit Ethernet,, Filtering and matching data and DMA transmission of PCI Express bus. A software verification platform of the system is built to test the functions of system. And the performance of the entire system is tested and analyzed in the hardware testing environment along with software drivers for system.Implemented on the Xilinx Virtex-5 FPGA chip, the access of four Gigabit( data stream of 4 Gbps ) Ethernet data, filtering and matching of the data stream through CAM chip, transmission of processed data blocks via PCI Express bus and sending processed data blocks to host server through DMA are achieved. The system offers a transmission rate of 3 Gbps for DMA.