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Based On Linear CCD Image Scanning Platform Research

Posted on:2012-06-07Degree:MasterType:Thesis
Country:ChinaCandidate:S L ZhangFull Text:PDF
GTID:2218330368486925Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
With the improvement of industrial automation, in the pipelining of the procedures, intelligent processing system to gradually replace the manual operations. It's hard for conventional products to meet the increasing requirements of real-time detection. Meanwhile, rapidly developed high-resolution sensors and reconfigurable programmable logic device features, provides a hardware platform for high-precision real-time processing.In this paper, chose linear CCD sensor and FPGA as the main devices, built a hardware processing scanning platform. Platform includes linear CCD sensor and control module, ADC module, the driver and control module, processing module and communication modules. In the drive and control modules, processing module using Verilog HDL to achieve between the sample and the sensor control, and meet the timing requirements of SDRAM memory and VGA display. Among them, the structure employs asynchronous FIFO to transfer data between different clock domains, effectively avoiding the appearance of metastable state. In addition, within Xilinx FPGA, a 32-bit embedded microprocessor Microblaze, servers, SPI interface for flash memory and the adaptive 10M/100M Ethernet interface for host computer communication.With the platform, use the method to achieve parallel pipeline image filtering, edge detection and edge flow region, so as to achieve the purpose of image scanning detection.During the PCB design, the smart software Cadence's schematic Capture & Allegro plays a key role, with considering signal integrity and power integrity. In the course of FPGA implementation, with the help of Mentor's Modelsim SE simulation prior to and after simulation, Xilinx's ISE completes logic synthesis, physical constraints and timing constraints, logic optimization, finally generates the bit files and configuration files which can be downloaded. FPGA configured modes also been considered thoughtfully, the master serial mode is a choice.
Keywords/Search Tags:Linear array CCD, FPGA, Verilog HDL, image processing
PDF Full Text Request
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