The Design Of Bayer Color Image Recovery Based On FPGA

As the wide application of the digital photography in fields such as aerospace, astronomy, the public security and medical treatment, the development of hardware and software system of digital photography also have caught more attention. With the quick development and wide application of very large scale integrated circuit and large-scale programmable logic devices, the real-time image processing has also been developed rapidly. in order to improve the speed of image processing, satisfy the system real time request, hardware is used to realize the image processing, and the chip is one of the best choices of target hardware. At the same time it also helps provide the new ideas and solutions to improve processing speed of image.Thesis mainly designs and explores the Bayer format color recovery system based on FPGA.Common middle-end color camera captures color images by covering a layer of color filter array on the surface of the CCD or CMOS image sensor, then interpolation algorithm That method of adopting color filter array cut down the digital camera’s cost and volume,but it also brought a problem, which is to choose what kind of method to get back most of the lost color information, to restore the image that can be most accepted by the human eye. The image shoot by image sensor covering CFA is referred to Mosaic images. The related process of restoring the Mosaic image to color image becomes to color image restoration or interpolation, or to the Mosaic. So far, many mature interpolation algorithm has been applied in various demands, such as bilinear algorithm, adaptive interpolation algorithm. Some of these algorithms are in some simple calculation and easy hardware implementation, but the interpolation is unsatisfactory; and some interpolation effect is good, but difficult to implement in hardware because of the computation complex. Facing the high-speed image acquisition system, people have been looking for a good method which can realize effect by using hardware. With the emergence and development of programmable logic devices, this kind of device has been found to have a great advantage in the aspect of image processing and it also can undertake the parallel processing algorithms on hardware, so using FPGA to realize image restoration system can realize the balance between the processing speed and image quality.This article first reviews some of the typical interpolation algorithm by comparing analyzes and summarizes the advantages and disadvantages of each method,and aims to the requirements for real-time processing,proposes an improved interpolation algorithm based on a method.Then in order to realize the algorithm, a hardware system is designed, the thesis designs the system overall scheme, including image sensors, image cache module, power module, control module, crystals circuit, configuration module, FPGA master control chip image acquisition and display module. In the design, it chooses the OV7725 Omni Vision sensor, design of PAM3101DAB250 regulated power supply, VGA video encoding chip ADV7123, Altera company’s Cyclone IV series FPGA chip EP4CE15E17C8 N, hynix HY57V283220 T as SDRAM chip. Finally it carries out simulation of the algorithm by using Verilog HDL, and implements the algorithm in FPGA. The FPGA implementation scheme of the designed new algorithm, puts forward the scheme of realization of data caching from the aspect of saving resources, proposes to calculate the implementation of the scheme from the perspective of improving processing real-time interpolation. By taking he Verilog HDL language as hardware description language and adopting FPGA chip from Altera Company, the design completes a new algorithm with high processing speed and low resource consumption. In the process of improving processing real-time, the design takes parallel processing and pipelining processing designing idea.This system design takes fully consideration of the system circuit miniaturization, lightweight and low cost and so on. Based on the FPGA’s a series of superior characteristics of miniaturization, modularization, flexibility,the design in this thesis uses FPGA software to achieve the purpose of function implementation, using the Verilog hardware description language. In addition, because of the characteristic of the repeatable wipe of the FPGA programming, it is convenient for upgrading equipment and correction. At the same time the images after color restoration is detailed in visual and the pseudo color has been effectively suppressed.