Research On Iterative Parallel Packet Interference Cancellation Algorithm For HSUPA

The evolution of WCDMA standard has gone from stable Release-99 (R99) to the Release-4 (R4), the Release-5 (R5), the Release-6 (R6), the Release-7(R7), the Release-8(R8).These versions of the upgrades are all forward compatible. New technologies based on the original version are proposed and HSUPA (High Speed Uplink Packet Access) is the most attractive one. As the channel demodulation performance is affected by the large channel power of HSUPA users, interference cancellation techniques are applied to elimilate the interference of HSUPA users.Serial interference cancellation and parallel interference cancellation are typical interference cancellation algorithms. Serial interference cancellation algorithm has better near-far resistance ability, lower implementation complexity and higher system performance. But it has the drawback of larger time delay. The performance is deteriorated with larger number of users. However, the parallel interference cancellation also has the defects of large implementation complexity. Therefore, combining the advantages of SIC and PIC, an iterative parallel packet interference cancellation algorithm is proposed in this paper.To begin with, the research background is presented, and the technical improvements of HSUPA based on WCDMA are summerized. The basic principles of the two typical interference cancellation algorithms (serial interference cancellation algorithm, parallel interference cancellation algorithm) are analyed in detail.Secondly, an Iterative Parallel Packet Interference Cancellation Algorithm is proposed, and the simulation results of the system-level and link-level are presented. The better interference cancellation performance under different channels is verified by performance of throughput within each cell and interference cancellation gains.At last, the processes of interference reconstruction and subtraction interference cancellation algorithm for the control channel and the data channel are introduced. The interference cancellation gain of the proposed algorithm can be achieved indirectly through the link-level simulation curves of block error rate and interference cancellation efficiency with designed system-level simulation parameters. The applications of interference cancellation algorithm on chip are verified.