The Design Of A Configurable IP Core For The IIC Protocol Controller

With the rapid development of FPGA, the formation of SOPC system was promoted. To communicate with external devices, extension is needed where serial bus has been used widely because of its simple structure. Most IP cores for serial bus controller are protected by intellectual property, so it is necessary to design IP cores for serial controller by which we can flexibly generate SOPC System.IIC bus has simply structure and less connection which is a bus protocol and used widely. Focusing on the frequency issues, the structure of configurable IP core for IIC bus protocol controller is proposed, which is completely compatible to IIC specifications and has the standard Avalon bus interface. The parameters are implemented by increasing a internal register, called configuration register. In the frequency selection, configure by the configuration register or direct input manner can be chosen. When configure by the configuration register is chosen, as long as frequency parameter is entered the frequency can achieve and make the input of frequency value more simply and easy.The IP core is divided into four modules which include IIC control module, parallel data transceiver module, serial data transceiver module, the clock module, and is prepared by Verilog language. Simulation and synthesis was carried out by using software. The simulation results show that the frequency parameters of configuration by the configuration register and the calculated result is consistent, have achieved the clock frequency following in the 63MHz and data transmission; The synthesis results show that resources of occupied meet the design requirements and the largest global clock can reach 260MHz. The IP core is verified by using Altera's FPGA. The results show that the result is consistent by comparing the data from the PC sends to the EEPROM with IIC interface with the date is read back.