Hardware Template Design And Reconfigurable Array Architecture Research Based On Video Compression Algorithm

With the widespread using of video applications, the traditional general processor and application-specific integrated circuit cannot satisfy the high performance demand of video application, the emergence of reconfigurable computing fills the gap between the two implementations, the array structure is especially suitable for algorithms with high computation-intensity and data-parallelism in video applications.This thesis analyzes AVS, MEPG-2 and H.264 video compression standards and chooses algorithms which is suitable for reconfigurable array. Based on reconfigurable multimedia processor REMUS and its compiler platform, the data flow graph is extracted and mapped on reconfigurable array RCA. The configuration words, which are called hardware templates, are generated manually. The comparison of these templates hardware simulation results and ARM7 processor software simulation results shows that the templates have enhanced speedup range from 14.60 to 42.22 and overall speedup rang from 1.095 to 1.235. This indicates that the reconfigurable array has good accelerating effect on these algorithms.Based on the analysis of RCA and hardware templates, this thesis proposes an improved architecture called V-RCA. V-RCA has re-designed PEs, enhanced interconnection capability and simplified data store and transfer mechanism. The results of algorithm mapping shows that the computing resources utilization of V-RCA is 2~8 times of RCA. With the same amount of PEs, the mapped nodes of V-RCA is 2~8 times of RCA. This shows that V-RCA has a better mapping efficiency. This thesis builds the RTL hardware model of V-RCA and synthesis it with TSMC 90nm process. The chip area is 1.38 mm2 and the frequency is 100Mhz。The results of algorithm simulation shows that V-RCA has the capability of 1080p HD video decoding. Using 2D-DCT as test algorithms, the hardware simulation results of V-RCA are compared with other architectures. The results shows that the area efficiency of V-RCA is higher than these architectures.