Research On The Design Technology Of Reconfigurable SoC

The market of PC tends to be saturated."Digital consumables", PDA mainly, will lead the next generation semiconductor product, the most apparent character of these digital consumables is the continual updating which will cause huge amounts of electronic landfills. Reconfigurable SoC combined the hardware high performance and software flexibility, which can be compatible with multiple protocols and simultaneously give user enough space for individuation and updating. Moreover, reconfigurable SoC can meet the time-to-market requirement of digital consumable products, and will drive the divide of"chip design"and"product developing".The design methodology and implement technology of dynamically reconfigurable SoC is researched. A compressing algorithm for FPGA bitstream is proposed, and the combination of reconfigurable SoC and Network-on-Chip technology is studied. The main work and achievements are as follows:1. Taxonomy of reconfiguration mode is proposed based on the conclusion and analysis of present research results on RSoC (Reconfigurable System-on-Chip) and SoPC (System on Programmable Chip). The future direction of reconfigurable SoC is discussed. A 3-D space of dynamic reconfiguration is built. A general architecture of dynamic reconfigurable SoC is presented, and its compute model and design flow are discussed. Three kinds of solutions of dynamic reconfiguration are proposed and illustrated, taking use of the Xilinx Microblaze-based SoPC and its development tools kit.2. An adaptive LZW algorithm for compressing global and partial bitstreams of FPGA is presented. The adaptations of algorithm are based on analysis of the three-level data regularity of the configuration bitstreams. Partial bitstreams are created through Xilinx module-based partial reconfiguration flow. The experiment demonstrates down to 45.63% compression rate for global configuration bitstreams and 43.69% compression ratio for partial configuration bitstreams of several real-world applications implemented on Virtex series FPGAs.3. A mathematic model of NoC based on irregular 2D mesh topology is built for reconfigurable device. The mathematic expression of grid overlapping constrain is presented, and the problem of calculating the communicating distance between IPs is resolved. The experiment with a video object plane decoder demonstrated the efficiency of the algorithm. An FPGA implementation example of placement result is given.