| Reconfigurable system is suitable for data-intensive applications due to the combination of flexibility and efficiency. Cipher algorithms need to deal with large amount of data. The combination of cipher algorithms and reconfigurable technology can meet the requirements of performance and security. To meet the increasing performance requirements, the block cipher reconfigurable system turns into large-scale process elements array. High function unit redundancy and low utilization are two main problems in the current cipher architecture design, which seriously impact the area efficiency of the whole system. This Thesis focused on reducing redundant functional units in the design of a cipher reconfigurable array by operator characteristics analysis and mapping algorithm analysis, which improved the area efficiency of the whole system.First, an AOV network analysis model for block cipher was established to extract algorithm features associated with architecture design. Then completed the initial design of PE array including the design of array topology, PE group, PE structure, interconnection unit and functional unit, according to the algorithm features extracted. Then, proposed the Algorithms mapping tools based on VF2 subgraph isomorphism algorithm using the graph models of algorithms and architecture as inputs. A set of block ciphers were mapped to the initial PE array design to find and reduce the redundant unit in the array by evaluating the functional unit utilization. From several rounds of this iterative, finally got non-unit-redundant PE array design.The circuit was realized finally under TSMC 40 nm CMOS technology, with the frequency of 500 MHz. and area of 0.22mm2.30 block cipher algorithms were selected as the test set. The average function unit utilization is 25.5%, which is 83.2%?168.5% higher Compared to the other block cipher reconfigurable design. Area efficiency is 171.7Gbps/mm2, which is 57.1%?643.5% higher. |
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