Research On Reconfigurable Compiler Oriented To FPGA

In recent years,FPGA(Field Programmable Gate Array)technology has been developed rapidly,which has become an important acceleration platform for intensive and big data computing applications owing to its low power consumption,configurable and highly parallelized features.The reconfigurable architecture based on the FPGA platform need the support of reconfigurable compilation system.Through the analysis of the current reconfigurable compilation systems,it is found that the reconfigurable compilation system still has many deficiencies,such as insufficient research on the run-time performance evaluation of the program,insufficient research on the hardware multi-version in the compiling process,the HW(hardware)/SW(software)partitioning granularity being simplification,insufficient support for the automatic mapping template for loop program optimization,the robustness and instructions parallelism of the compiled hardware codes needing to be improved,etc.Therefore,the quality of the program compilation can be further improved through solving the above problems.The above problems can be solved through studying the critical technologies of reconfigurable compiler in the thesis,which include the compiler architecture design,the program run-time features evaluations,the selection scheme of HW/SW partitioning granularity,the analysis of hardware multi-versions,the HW/SW partitioning model,the automatic mapping template of parallel structure,the mapping and optimization scheme for IR(intermediate representation)codes.The specific research work in the thesis can be divided into the following parts:(1)A reconfigurable compiler framework oriented to FPGA is presentedThe core functionalities of compiler framework are implemented by LLVM(Low Level Virtual Machine)system.The LLVM is used as the front end of the framework to realize pretreatment of the input code and produce IR code.The IR code is partitioned by the HW/SW partitioning model of the thesis.And then,the IR code is repackaged to software functions and hardware functions according to the partitioned result,and the interface auxiliary information file is produced.After that,the hardware IR functions are optimized and transformed,the HW/SW communication interfaces are generated,and the software IRfunctions are decompiled to produce software C code.Finally,the EDK(Embedded Development Kit)and ISE(Integrated Software Environment)are used as the back end to generate the software and hardware running code of the target system.The main differences with other compiler frameworks include: the independent function library is established to deposit the module being called by the compiler framework which will facilitate upgrade and improvement of the compiler framework;the HW/SW partitioning model is implemented based on the program run-time evaluation,variable partition granularity and hardware multiversion.The experiment results show that the program can be compiled correctly to HW/SW cooperative system by the framework.(2)A HW/SW partitioning model based on program run-time characteristics and hardware multi-version is presentedThe HW/SW partitioning model is presented according to the existing problems in HW/SW partitioning.According to the flow chart of HW/SW partitioning model,firstly,the program run-time characteristics evaluation module is designed which include the software execution time evaluation model based on the BP(back propagation)neural network and the hardware overhead evaluation algorithms based on the analysis of IR operation instructions.The hardware overhead evaluation algorithms include the selection scheme of HW/SW partitioning granularity,the analysis of hardware multi-version,the hardware execution time evaluation algorithm,the hardware area cost estimation algorithm and the communication time calculation method between hardware and software.The weights of hardware related evaluation formulas should be modified by the runtime feedback information of the compiled system because of the difference of target hardware platform.Finally,the HW/SW partitioning model is designed and realized based on the above researches and improved GA(genetic algorithm).The experiment results show that the program run-time characteristics evaluation algorithms can achieve more accuracy results and can satisfy the requirement of the HW/SW partitioning model.Applying the HW/SW partitioning model can achieve better acceleration effect than similar studies and the convergence of the HW/SW partitioning algorithm is obviously improved by modifying the GA operations.(3)An automatic mapping template from cyclic code to systolic array structure is presentedAn automatic mapping from cyclic code to systolic array structure template is definedaccording to the characteristics of regular cyclic code and systolic array structure.The template uses DDM(data dependence model)as input.Firstly,the global data dependencies are eliminated by automatically adding temporary variables.Then,the DDM is mapped to the VSAAM(Virtual Systolic Array Architecture Model)through the spatiotemporal mapping functions.Finally,the VSAAM is synthesized to RSAAM(Reconfigurable Systolic Array Architecture Model).RSAAM is the final systolic array structure template.The template can provide a way to implement a hardware version for reconfigurable compiler framework.The experiment results show that the automatic mapping template can achieve less system execution cycles than the similar studies and higher speedup than the software execution,but it will consume more hardware resources because of the reconfigurable interface unit and many temporary variables being added.(4)An IR code mapping and optimization scheme oriented to hardware is presentedAn IR code mapping and optimization scheme oriented to hardware is designed according to the hardware execution features of FPGA.Firstly,optimization schemes oriented to semantic to prevent the accessing memory conflicts and data type mismatching are designed.And then,optimization schemes oriented to hardware to parallel the IR instructions are designed.Finally,the mapping from IR code to VHDL code is realized,and the corresponding data read/write control logics are generated.The experiment results show that the mapping from IR code to VHDL code can be realized correctly by applying the mapping scheme of the thesis.The robustness and the instruction parallelism of the hardware code can be improved by optimizing IR code under the premise of keeping the original operation logic unchanged.So the execution efficiency of the compiled system is improved.The critical technologies researched in the thesis have been applied to the functional modules of the reconfigurable compiler framework.The experiment results show that the corresponding problems existed in the reconfigurable compiling system can be well solved by applying the research results of the thesis.The better system acceleration effect can be achieved by applying the reconfigurable compiling framework of the thesis.