Implementation And Mapping Of A Typical Video Decod-ing Algorithm On A Reconfigurable Computing Processor

Reconfigurable computing processors are composed of embedded pro-cessors and reconfigurable cells array, featuring the advantages of the highperformance of ASICs and the flexibility of general-purpose processors.With the capability of parallelly processing complex algorithms, reconfi-gurable computing processors become an effective way to solve the diversi-ty needs of multimedia processing. Based on the similarities and characte-ristics of multimedia algorithm, this thesis proposes the method of hard-ware and software partitioning and realizes H.264decoding algorithm onthe reconfigurable multi-media system.The main works and achievements of this dissertation are as follows:With the research of the principle of H.264algorithm and the architec-ture of reconfigurable multimedia system Remus, the paper extracts thecharacteristics and commonalities of multimedia algorithms.Based on thecharacteristics of the algorithm, such as data regularity, heavy computationand large amount of loop operations, this paper proposes the implementingmethods of algorithms on the Remus reconfigurable processor.The motion compensation, intra prediction and inverse discrete cosinetransform of the H.264algorithm are mapped on the reconfigurable cell ar-ray. The method of hardware and software partitioning is also introduced.The simulation and verification are performed for the reconfigurablesystem. The performance of assessment proves that the system can support1920x1080@30fps real-time decoding of H.264at200MHz.