The Design Of Low-power High-precision Analog-to-digital Converter In MIMU

In recent years,with the continuous advancement of integrate d circuit design technology and manufacturing process,MEMS sensor technology has also developed rapidly.As a bridge connecting the sensor and the digital signal processing unit,the performance of the analog-to-digital converter(ADC)largely determines the performance of the entire system.This makes high-performance ADCs the focus of research at home and abroad.Aiming at the low-power and high-precision ADC performance requirements of the micro-inertial measurement unit,combined with the advantages of sigma-delta ADC precision and SAR ADC high energy efficiency,a continuous-time sigma-delta based on SAR quantizer is given Modulator design.First,the topology of the continuous-time modulator is determined from the perspective of low power consumption.According to the performance index of the subject,the function of the toolbox is used to complete the design of the modulator noise transfer function,and the zero-order feedback path is added to repair the noise transfer function that changes due to the loop delay.Then,the coefficients of the modulator are reasonably scaled so that the output of the integrator conforms to the actual situation.Finally,Simulink was used to build behavioral simulation models for the non-ideal characteristics of integrator,clock jitter and feedback DAC.After considering the non-ideal factors,the circuit parameters of each module were determined,mainly to determine the parameters of the operational amplifier in the integrator circuit.In the selection of the structure of the multi-bit quantizer,this paper selects the SAR ADC based on the sampling of the capacitor top plate.Compared with the traditional structure,this structure reduces the capacitance of the sample and hold circuit by half,and also reduces the number of capacitor charge and discharge during the conversion process.In order to avoid the us e of high-frequency clock generators,an asynchronous control circuit is designed to generate clock signals for internal circuits.Aiming at the problem of excessive number of unit current sources in the current steering type feedback DAC,a first-order digital sigma-delta data truncator is added after the multi-bit quantizer to reduce the number of current sources,and the signal-to-noise ratio will not decrease significantly.Finally,the SMIC0.18 um process is used to complete the circuit design of the entire continuous-time sigma-delta modulator.The circuit simulation results show that the modulator consumes 0.98 m W of power at a voltage of 1.8V.From the spectrogram,it can be concluded that the signal-to-noise ratio of the modulator reaches 104.4d B,and the effective number of bits is 17.05.After considering the thermal noise,the noise floor is lower than-120 d B,the harmonic distortion is less than-100 d B,and the dynamic range in the 100 Hz bandwidth is greater than 110 d B.