Design And Implementation Of High Speed Data Acquisition System For Radar Altimeter Echo Wave

This thesis introduces a kind of high-speed data acquisition system based on the Compact PCI bus, the system is designed for the real-time acquisition of high speed echo wave from pulse radar altimeter, it can also be used for other general occasions of data collection. The system provides a sampling rate of up to 200MSPS, a quantize precision of 12 bit, and achieved less than 0.3% of the analog signal static distortion.Currently, the difficulty in design and implementation of high performance data acquisition system design does not lie in the high-speed analog signal sampling, but in the section of real-time data processing, transmission, and storage; traditional storage media often have deficiencies on speed or capacity, and speed of data transmission to computer system transmission is also limited by several factors, such as bus speed of computer system and response latency of operating system, these are the main bottlenecks that limit the performance improvement of data acquisition system.After much study and analysis, the subject decide to use FPGA to complete the real-time data processing task, a multi-level cache system was then designed to achieve the fit between sampling data from high speed ADC and Compact PCI bus, then a 32bit/33MHz configured Compact PCI bus and a RAID0 configured disk array system were used to achieve real-time high-speed data transmission and storage.This paper first introduced basic principles and structure of data acquisition system, and designed main architecture of the system based on the requirement, then analyzed and calculated main parameters of the system; meanwhile, it introduced the details on the hardware design, FPGA logic design, drivers and application program design under the Windows operation system. According to the interrupt response characteristics of the operation system and Compact PCI bus, the operating principle of FPGA and off-chip FIFO based high-speed multi-level data cache system was explained, along with the high efficiency data split and reorganization mechanism.