Research On The Key Technologies Of Boundayr-Scan Modeling

As the development of electronic technology, the structures of chips are getting more and more sophisticated; the arrangement of the pins has become relatively compact and the internal logic turns out to be more complex than ever before. The difficulty in testing large-scale integrated chips has consequently been enlarged extremely, which requires testers to provide a more simple and accurate method of troubleshooting and chip maintenance. This paper, targeting the new characteristics of IC testing, studies circuit test method that was based on boundary-scan technology and establishes the models for key technologies such as memory testing principles and interconnection testing. A boundary-scan software program has also been developed. All these contributions will fix the drawbacks of traditional testing methods and appear absolutely applicable.Researches completed on boundary-scan modeling are as follows:First, a comprehensive blueprint has been proposed on the basis of desire analysis to boundary-scan software. Layered and modularized structures are adopted in this design and based on which software for each of the modules is developed using C language. According to the characteristics of test objects, testing models are established after deep analysis in the perspectives of testing principle, algorithm, fault model and troubleshooting methods. Benefited from proper arrangement and software design, modeling of different layers for boundary scan software is accomplished.Secondly, this paper provided models for memory and interconnection on the basis of fundamental boundary scan principles and further research in its testing methods. Memory testing can be categorized into three models including memory information model, memory fault model and memory algorithm model. Interconnection testing is classified as interconnection structure model, interconnection fault model and interconnection algorithm model. The performances of various algorithms are compared and an improved one has been proposed.Finally, a boundary-scan testing software system is built based on previously mentioned key techniques and the testing models and methods have passed the experimental tests. The testing IC and the verifying platform are also built in relate to third party PC programs. Models for memory and interconnection, which are the two main test objects, are substantiated after fault simulation. The experiments revealed that methods and models within this paper are remarkably effective in testing large-scale integrated digital chips and diagnosing troubles.In sum, the boundary-scan testing software designed in this paper is advantageous in testability, generality and expandability. It operates efficiently on faults diagnosing and therefore research in key techniques of boundary scan testing modeling is proven worthwhile in practice.