Modular Design And Implementation Of Multi-Channel NAND Flash Controller

Due to restriction of the mechanical operation, traditional mechanical-electrical Winchester hard disk drive has encountered the performance bottleneck. However, a new storage device named solid state drive has a very promising future, which not only refers to the prospect of market acceptance and popularity, but also means the promoting of the performance.After working principles of NAND flash chip including storage structure and chip operations have been studied in details, the instruction sets to be implemented as well as the timing sequence to be met are determined. The bus architecture of multi-channel flash controllers system is proposed, making use of multi-channel techniques such as interleaving, stripping and pipelining. The module of flash controller consists of four functional modules, which are command parsing module, state machine controlling module, sampler module and data path module. Programmable FIFOs built within the FPGA are used for buffering the data between multi-clock domains, while the input/output blocks are applied to implement the two-way tri-state data transmission. Timing problems existing in the design are corrected by the functional simulation.After logic verification, the flash controller is implemented with field programmable gate array (FPGA). After the system-level hardware platform is built up, flash controller is encapsulated into an IP core, which is connected to the process local bus. The registers within the core send out commands and data signals simulating the host interface, which directs the flash controller to complete the command operations. Test results show that the flash controller can achieve the operations of erasing, programming, reading and so on, correctly.