Using UVM And Direct Programming Interface To Improve The Reusability Of IC Verification

With the continuous progress of IC manufacturing process and IP integration technology,the structure of IC chips is more and more complex,the chip development cycle is longer and longer,and the difficulty of verification is also higher and higher.Due to the zero defect tolerance of the chip and the high cost of laminating,comprehensive verification is required before laminating.It is very important to improve the quality of chip verification and shorten the verification cycle.Traditional verification methods have been unable to meet the needs of chip verification,At this time,In order to solve the above problems,UVM(Universal Verification Methodology)has emerged.Generic Validation Methodology is a validation platform development framework based on the System Verilog class library.Validation developers can use its reusable components to build a functional validation environment with standardized hierarchies and interfaces.UVM is a new generation of validation methodology jointly launched by Cadence,Mentor and Synopsys,three major EDA manufacturers.It has become the standard in the field of validation.Compared with traditional verification methods,its most prominent advantages are the reusable verification environment,the generation of constrained random excitation and the application coverage driven strategy,so as to effectively improve the integrity and efficiency of IC verification.Since the introduction of UVM methodology,there have been a large number of experts and scholars at home and abroad have carried out in-depth research and application on UVM in various aspects.However,there is a common problem in all the above studies: the established verification platform can only realize the reuse of verification environment,but cannot realize the reuse of test cases.Therefore,I think it is very necessary to conduct detailed research on the reuse of test cases,so as to improve the efficiency of IC verification and shorten the chip development cycle.Aiming at the problems in the research and application of UVM described above,this paper proposes a scheme to improve the reusability of IC verification.The scheme used UVM and direct programming interface technology,implementing general verification methodology and C language program of interactive communication,not only reduce the complexity of general verification methodology used,and makes the C language test cases can be transplanted in different test level reuse,for example C test code can piece from the integrated circuit module level to system level of reuse.In order to verify the correctness of this scheme,this paper takes SPI controller as an example,and uses Mentor's Questa Sim version 10.6c simulation software to build its UVM verification platform under Linux system.It then develops its large number of UVM and C test cases,and quantifies the validation progress through coverage.Experimental results:After each test case runs,the true value of the data is the same as the expected value;The verification report generated by Questasim is correct without errors;The functional coverage reached 100% of expectations;The most important thing is to add virtual processor in the experiment to ensure that C test cases can be run correctly from IC module level to system on chip level,so as to achieve the purpose of reuse of test cases.The experimental results show that the reuse of UVM environment and test cases can be achieved,so as to improve the reuse of integrated circuit UVM verification and shorten the chip development time.