Design Of Digital Post-Processing Circuit Based On SIGMA-Delta Modulator

In recent years, the digital integrated circuit technology has been developmenting rapidly, its strengths, such as high precision, high speed and anti-interference ability, have been widely used in various fields. As the connection between the fields of analog areas and digital areas - Analog to Digital Converter (ADC) has also become a hot research along with the development of digital technology. Sigma-Delta ADC earned much attention in signal processing field because of its high precision and low noise. In the Sigma-Delta ADC, the modulator determines the precision and the conversion rate of the system, as well as the digital decimation filter for the whole chip area and power consumption. At present, low-cost, low-power IC design is the constant pursuit of today's chip designers. During the Twelfth Five-Year-Plan period, the MEMS Central Laboratory of Harbin Institute of Technology focus on the development of digital sensors, so this paper managed to design a high performance digital decimation filter.This paper designed a digital decimation filter whose over-sampling rate is 256 and cut-off frequency is 1K. It is three filter cascade with the output of 24bit. The filter is applied to 4-order micro-capacitor Sigma-Delta modulator accelerometer interface circuit. The decimation filter includes: cascaded integrator comb filter, compensation filter and half-band filter. The design of cascaded integrator comb filter uses recursive structure, so that the circuit compact, the occupied chip area smaller. Compensation filter which combines the emending phase of FIR filters with a half-band filter together has the functions of down-sampling and compensation the pass band attenuation. This results of low cost of hardware and power savings. Compensation filter and the half-band filter both use the direct symmetric FIR structure,and also the coefficients of them are realized with CSD (Canonic Signed Digit) code,both results are smaller chip area and lower power consumption.The project makes use of Matlab for system setting up, Modelsim for writing RTL code. It uses the output of the voted 4-order micro-capacitor Sigma-Delta modulator accelerometer interface circuit in the laboratory as an incentive signal to write the test vectors for functional simulation. Then use Altera FPGA to realize the hardware verification. Afterwards, synthesis and layout with the related technology library, and submit circuit layout. Ultimately, the result of the overall design has good performance, it achieved the function of the digital decimation filter and met the expected target.