Design Of Charge-Pump Phase Locked Loop In Micro-Inertial

For the advantages of its low-power, low-jitter, high speed and easier realization in practice, charge-pump phase-locked loop (CPPLL) is used in many fields. It has important practical significance for improving the accuracy and stability of the micro-inertial device that using the technology of PLL for the micro-inertial deice drive circuit to provide and maintain accurate and stable frequency signals.This paper expounds the working principle of each module that constitutes CPPLL, linear model of the CPPLL system and the important performance parameters after a detailed description of the PLL system's basic principle. And the noise characteristics are also studied in this paper. Based on these academic analyses, all the modules'circuit of the CPPLL are designed and simulated. This paper presents a phase frequency detector (PFD) that has stable performance, high precision and no dead zone; charge pump (CP) is designed with current mirror that could improve the matching of the charge and discharge current and the use of unity gain amplifier rejects the charge sharing; A differential ring voltage controlled oscillator (VCO) with four delay cells is selected and a good linearity near the center frequency is obtained by a large number of simulations and the parameters adjusting. The important parameters of PFD,CP and VCO are used to calculated the value of low pass filter (LPF).; Through the behavioral level simulation of the system, the system of CPPLL is optimized. At last , the circuit simulation, the design and simulation of layout are completed.The design and simulation of this thesis is based on the 0.5μmCMOS existing process library in laboratory. The system works at the 5V supply voltage, and the simulation results show that when the input is 10kHz square wave signal, the system set-up time is about 6ms, the output signal frequency jitter is about 0.186Hz, the frequency stability precision of 0.186/10000, periodic jitter 931.32ps, and static power consumption is about 6.3mW. The system's phase margin is 53°, -3dB bandwidth 1.09kHz obtained by calculating. Post-layout simulation results show that when the input is 10kHz square wave signal, the system set-up time is about 9.72ms, the output signal frequency jitter is about 0.286Hz, the frequency stability precision of 0.286/10000, periodic jitter 1.87ns, By contrast with circuit simulation results, post-layout simulation results show that because of the parasitic effects the PLL system performance degrades to a certain extent, but still meet design requirements.