Microprocessor Pll Design

This paper designed a microprocessor used as a clock-driven high-performance charge pump phase-locked loop (CPPLL) circuit, The design uses standard CMOS charge pump phase-locked structure, including Phase Frequency Detector(PFD), Charge Pump(CP), Low Pass Filter(LPF), Voltage Controlled Oscillator(VCO) and Frequency Divider(Divider) five modules. In a detailed analysis of the internal structure of the phase-locked loop and the basic principles on the basis of its research phase noise characteristics and properties of loop, and carried out the Simulation of it. At last, draws the layout.The design employs the standard CPPLL structure, comprising a phase frequency detector, a charge pump, a low pass filter, a voltage controlled oscillator and a frequency divider. In order to achieve the optimization of the whole CPPLL, the design employs a plurality of novel structures of a phase frequency detector, a current-mode charge pump, a voltage controlled oscillator with two-stage differential negative resistances, a current-mode filter, and a TSPC frequency divider, wherein, the phase frequency detector can effectively eliminate the dead zone. The current-mode charge pump structure has low power consumption and high charge or discharge velocity, and well inhibits the charge sharing effect. The voltage controlled oscillator has wide oscillating range and low noise, the current-mode filter circuit has low noise and low power consumption, and the Master-slave frequency divider has fast operational speed.The simulation result shows that when the ideal clock source being the reference signal in the design, the system locked time is 97.891μs, the central oscillation frequency is 533MHz, and the jitter of the output frequency is low. The frequency jitter isΔF p?p, that is 87.721Hz between the time of ambient temperature at -55℃~ 125℃change, and the cycle jitter 4.289ps; relative jitter 0.002144‰.The power consumption of the circuit is 30mw. In the design, the output frequency has better stability under high frequency, relative short locked time, and low power consumption.