Design Embedded SoC For DDC Application

Software radio technology is now widely used in wireless communication systems, and more wireless communication devices are used in people's lives. The idea of software radio is to make the analog digital converter as close to the RF front end, then output digital signal, so that subsequent frequency filtering, modem, communications protocol processing, can be processed by digital circuit and software. Digital down conversion circuit is one of the core technology of software radio, it will sample IF digital signal to the low-frequency digital signal. DSP or microprocessor can process the baseband signal.In this paper, we design and implementation of an embedded SoC for the application of DDC. SoC design methodology is based on platform; each module in the system is transferred from the existing IP core. By this way we can speed up the system design, and improve the success rate of design. The SoC use open source OpenRISC processor, and use wishbone bus connect IP modules, storage devices and IO peripherals. SoC use a dedicated DMA channel sample the continuous DDC output data and storage, reducing bus operation, improving system performance. OpenRISC processor executes the software algorithms processing DDC output baseband signal.When completing the design of SoC platform, do the system RTL simulation, validating the system function, the data transmission between modules and cooperation. In this paper, we use hardware and software co-verification way to verify system functionality. Write C language programs, compiled to binary code executed by the CPU to generate test stimulus. FPGA has good flexibility and speed. In this paper, we use FPGA to implement the system hardware prototyping platform, running a large number of software programs to verify the function of SoC. After the completion of RTL simulation, then use Xilinx's ML510 FPGA development board implement a system prototype for verification.When finishing the front-end SoC design and verification, use EDA tools to do logic synthesis, timing analysis, formal verification, P&R, physical verification, post-layout simulation etc. At last we generate SoC layout file. The SoC use Jazz Semiconductor's 0.18μm SiGe BiCMOS technology library to implement and the chip is running at 100MHz, area is 3.3×3.3mm2, power consumption is 154.3mW.