Research And Fpga Implementation Of Mixed Digital Signals Separation And Direct Digital Down-conversion

With the development of communication technology,a large number of communication systems and the limited spectrum resources cause the problem of spectrum aliasing to become increasingly serious.The Direct Digital Down-conversion(DDC)technology can separate the spectrum-non-aliasing signals only.How to separate spectrum-aliased signals is the problem that needs to be solved in this thesis.The solution of the problem is of great value in improving the spectrum utilization of the communication system and solving the shortage of spectrum resources currently.A feasible scheme is proposed for spectrum aliasing signals,that is,combining FastICA algorithm with DDC technology.The FastICA algorithm is used to separate the useful signal from the received spectrum aliased signals.The Direct Digital Down converter is used to reduce the sample rate of useful signal.Firstly,the principle of the independent component analysis algorithm and detailed steps of the FastICA algorithm are described in this thesis.Secondly,the realization architecture of the DDC and the principle and design method of key modules,such as NCO,CIC,HBF,FIR are introduced.Finally,basing on the case of second generation of Beidou satellite communication system,the FastICA algorithm,Direct Digital Down converter,and an integrated system of both FastICA and DDC are built under the Simulink environment of the MATLAB platform to simulate and analyze the results.After the simulation results meet the design criteria on MATLAB,Xilinx's VC707 evaluation board and latest EDA software,Vivado are used to verify the overall system in this thesis.The principles and design of several key modules and overall structure of FastICA algorithm are introduced in detail.After that,FastICA algorithm is simulated to determine the correctness of the algorithm's verilog code.Since most of modules of the Direct Digital Down-conversion have ready-made IP cores,this part is implemented by using the IP core integration method,then simulate the design and analyse of the results.By combining FastICA and DDC,the overall system implementation structure is introduced,the performances of the entire system in FPGA are analysed.Finally,the entire system is implemented in the FPGA development board and analysis results show that all design specifications are met.