Design And Implementation Of Data Receiving System For Optical Analog-to-Digital Conversion

Analog-to-digital conversion (ADC) is the key component of dataacquisition. It converts the analog signal to digital signal to be easily storedand processed. With the development of electronic technology, theperformances of electronic ADC (EADC), such as the sampling bandwidthand effective number of bits (ENOB), have been continuously improved.However, EADC still could not meet requirements in the field ofcommunication which analog signal bandwidth is growing fast. Due to“electronic bottleneck”, especially the electronic sampling clock jitter,EADC is unable to directly sample the ultra-wideband signal without anydistortion. Photonics technology has the advantages of ultra-wideband,high-precision, low jitter and high stability. Using photonic technology toprocess the signal in optical domain makes it possible to overcome theelectrically sampled bottleneck and significantly improve analog-to-digitalconversion performance, which is an effective way to increase thesampling rate and ENOB for ADC.In order to process and display the big data flow followed by greatlyincreased bandwidth and ENOB in OADC, the back-end receiving systemshould have the capability to store and transmit data which is high rate andbig capacity. This thesis design and implement the scheme of datareceiving system for Optical Analog-to-Digital Conversion, including data storage and transmission. The scheme adopts architecture of FieldProgrammable Gate Array (FPGA) with storage mediums of DDR3SDRAM and PCI Express external transmission bus using Direct MemoryAccess (DMA) mechanism.Firstly, the common hardware architecture of data acquisition systemis compared and analyzed. Based on layout of EADC in back-end opticalanalog-to-digital conversion and performance of FPGA, we design thehardware architecture with single-core and master-slave core. We alsodesign the logic architecture of storage control for DDR3SDRAM andtransmission control for PCI Express application layer. In this chapter, weelaborate the workflow for the storage and transmission logic and developa frame format for master-slave FPGA data communication.Secondly, we write all the codes for storage and transmission logicbased on FPGA after analyzing the design principle of storage logic anddescribing the workflow in all modules’state machine.Finally, we construct DDR3SDRAM memory model and PCIExpress transaction model to simulation the logic function. Under thecorrectly function, a test environment is setup which consist of singlechannel data receiving system and PCI device driver in Linux platform.We test the performance under the environment with storage andtransmission’s bandwidth and delay. The test results show that thebandwidth efficiency of storage logic is close to100%, and transmissionlogic is81.4%.