| Memory controller is an inportant part of the SoC chip., Its function and performance determines the SoC supported by external Memory types as well as external memory access speed. AMBA bus has become on-chip bus criterion of truth one, Design based on the standard of AMBA bus memory controller has better suitability , Support for different types of memory is also the basic requirement of memory controller.This thesis introduces the design of a memory controller based on AMBA bus, It can support multiple types of synchronous and asynchronous memory. This design can be used for reference the Rudi general deposit controlled system structure and PrimeCell general deposit control system structure characteristics According to the actual need of the project , Proposed the overall design scheme of EMI based on AMBA -AHB bus standard .EMI by AHB bus interface unit, command decoding unit and storage interface unit composed, Bus interface can handle AMBA-AHB bus agreement by accepting bus commands and can through bus fulfill data exchange; Command decoding unit realize bus command to storage interface command conversion; Memory interface unit will be different types of memory control logic separated into two types, synchronous and asynchronous respectively is controlled. Synchronous memrory control realization of SDR-SDRAM and SBSRAM control logic ,asynchronous memrory accused of supporting ASRAM, ROM, FLASH etc memory control.EMI realize read and write accessing memrory which support width of 32b,16b,8b. EMI design adopted in asynchronous FIFO, support bus hosts have reply based on SPLIT transmission mechanism,which improves the bus utilization.This paper conducted EMI RTL design and implementation, validation, logic synthesis and time-series validation optimization. Based on the Smic65nm standard unit library process. EMI realizes the external biggest 250MHz clock frequency, area is 93600um2, power consumption for 3.633 mW. It carry out logic validation and FPGA design validation. Result shows that this design of external memory interface functions correctly, has the very good compatibility, ability and industrial standard of memory seamless connection, meet the design requirements. |
