The Analysis And Realization Of High Performance Memory Interface Based On AMBA Bus

In SOC (System on Chip) design, the memory access latency is the whole system bottleneck due to small cache size and simple memory hierarchy the SOC usually employs. Situation is worse in some particular SOC design, such as the streaming media processor, which's low data locality ensures extremely low cache hit rate. The design of the SOC MEMC (memory controller) will then be decisive for memory access performace and thereby the over all system performance with given DRAM physical characteristics.The author of this thesis first establishes the significance of DRAM memory access speed through reviewing evolution of common SOC architecture, on-chip bus protocol, and the technical advancement and mainstream products of the semiconductor memory. Then the author summarizes possible MEMC optimization techniques by analyzing specific bus protocol and DRAM memory access characteristics. Based on this in depth analysis, the author designed and verified a SOC memory controller tailored for widely used AMBA bus protocol and the mainstream DDR DRAM.