Study On Design Optimization Of YHFT-DSP's On-Chip Memory System

Digital Signal Processors have been developmented fast and applicated widely after being invented. The organization of on-chip memory system affects DSP's performance a lot. Although the use of Cache has many drawbacks, for example, the cache miss delay is difficult to predict, and the real-time demand can not be well satisfied, it is still one of the key techniques for high performance DSP design due to its terrific harmonization with DSP algorithms. So researches on cache-based memory system for DSP are of great significance.The DSPs of YHFT-Dx series adopts the architecture of "On-Chip RAM and two-level Caches", which combines the advantages of RAM with those of Cache and has good extensibility, though data transferring between inner and outer chip is of low efficiency and the cache miss delay is still too long. Based on deep analysis of memory architecture on current mainstream high performance DSP and the characteristics of YHFT-Dx memory system, this paper raises many optimizing measures such as enlargeing the memory and optimizing the interface protocol, then implements, verifies and evaluate those methods in design.According to the characteristic that the second level memory can be configured to Cache or RAM, we enlarged its size directly from 64KB to 256KB but the additional 192KB was functioned as RAM only. This makes it possible to contain more code and data by enlarging RAM, consequently the miss rate of second level memory is reduced. Evaluation indicates that the performance of the memory system is improved by about 15%. In order to reduce the miss delay of L2 cache of YHFT-Dx, we further optimized the interface protocol besides adding a direct path from L2 to EMIF. We also set write buffer and adopted 'Requested Word First' technique between data cache and L2, between EMIF and L2, all of which improve the performance of cache system. These methods improve the performance of YHFT-Dx memory system by about 9%. The privileged read mechanism based on the offset of cacheline address reduces the cache miss delay and makes it certain.Given the inefficient EDMA data transferring between inner and outer chip, we optimized the I/F protocols among L2, EDMA and EMIF. By adding buffers, we implemented the pipelining of EDMA reads/writes which enhances the parallel processing ability and hides the memory access latency. This improves the EDMA data transferring efficiency by 60%.Complete benchmarks for the optimization to ensure the correctness of design was developed and the function and timing verification were accomplished. All these optimization techniques have been put into practice in YHFT-D4B.