| Compiler design for digital signal processors has traditionally been an art as opposed to production science; with conflicting tensions resulting from instruction set compliance, high performance expectations, efficient use of the hardware features, code compactness, and low power constraints. Along with the above are long time to market and verification hurdles. In this dissertation, a systematic methodology of retargetable code generation for digital signal processors has been developed that includes a high-level algorithm specification phase, a model-based hierarchical processor representation phase, and a DSP-specific multi-tier optimization phase. The combination of these three phases enables automated generation of assembly code whose performance is comparable to hand optimized assembly. The methodology promises correctness of the design results, within a short time to market, as opposed to other contemporary approaches, for digital signal processors. The developed methodology is verified through examples of efficient code generation for different DSP/Telecom applications, targeting multiple state-of-the-art digital signal processors. |
