Investigation Of Iniregrating Cu Film With Oxide Ferroelectric Capacitors On 51 Substrate

With the development of very large scale integrated circuit (VLSI), increasingly greater density of IC and higher performance of memories are needed, but the traditional interconnect technology and magnetic memories can't meet the requirements. Interestingly, Cu interconnects and nonvolatile ferroelectric random access memories (FeRAMs) are viable alternative for satisfying the need due to their advantages. Currently, in a FeRAM cell, the drain of a transistor must be electrically in contact with the bottom electrode of ferroelectric capacitor through a poly-Si plug or Al interconnect wire/diffusion barrier heterostructure, which has failed to meet the requirements of very small feature size, higher device density and wonderful performance of VLSI. To achieve more advanced memory technology, Cu thin film wire will be incorporated in ferroelectric memory by replacing Al as the interconnect wire between the drain of a transistor and the bottom electrode of ferroelectric capacitor in 1T-1C based memory architectures in order to make memory devices of high performance satisfying the development of the modern society.Several kinds of ferroelectric capacitors with Cu thin film, including Pt/SRO/PZT/SRO/Ni-Al/Cu/Ni-Al/SiO2/Si,Pt/LSCO/PZT/LSCO/Ni-Al/Cu/Ni-Al/SiO 2/Si, Pt/SRO/BFMO/SRO/Ni-Al/Cu/Ni-Al/SiO2/Si, have been fabricated using magnetron sputtering and sol-gel method with PZT or BFMO as dielectric layer and SRO or LSCO as electrode material by inserting two Ni-Al layers as barrier between Cu and SiO2/Si, Cu and oxides electrode, coinstantaneously. Furthermore, the microstructure, transport properties, the electrode quality, interfaces and ferroelectric properties of the samples were respectively investigated by X-ray diffraction measurement (XRD), four probe methods, atomic force microscopy (AFM), transmission electron microscopy (TEM) and a precision LC unit from Radiant Technologies. And the thermal stability to test temperature and key preparation craft of samples were studied. In addition, Cu/Ni Al-N/SiO2/Si heterostructure is prepared by reactive magnetron sputtering with Ni-Al incorporated N as barrier layer, and the transport properties, microstructure, surface morphology, failure mechanism and the activation energy of samples were evaluated.It is found that the SRO/Ni-Al/Cu/Ni-Al/SiO2/Si hetrostructure possesses strong Cu diffraction peaks and smooth surface at the annealing temperatures up to 750℃. Two crafts were investigated, including "Growth at the room temperature and then annealed at the high temperature" (GRT-AHT) and "Growth at a lower temperature and then annealed at the high temperature" (GLT-AHT), GLT-AHT is superior to GRT-AHT when the multilayer hetrostructure with Cu and oxide was fabricated since this method can relax stress, impair interfaces roughness and avoid to deteriorate barrier and Cu film at the high temperature.The PZT/SRO/Ni-Al/Cu/Ni-Al/SiO2/Si stack is analyzed by TEM. It is found that amorphous Ni-Al (a-Ni-Al) has been used as the diffusion barrier to prohibit reaction or interdiffusion between Cu and SiO2/Si owing to its lack of the grain boundaries as diffusion paths, meanwhile, a nanocrystalline Ni-Al (n-Ni-Al) and a-Ni-Al mixed film has been applied as oxygen barrier to protect Cu film from oxidation or reaction to aim the relaxation of stress through crystallization region in Ni-Al film, simultaneously, and to stuff the grain boundaries using the amorphous matrix surrounded crystalline grains.It is also found that the ferroelectric capacitors integrated with Cu, such as SRO/PZT/SRO/Ni-Al/Cu/Ni-Al/SiO2/Si,LSCO/PZT/LSCO/Ni-Al/Cu/Ni-Al/SiO2/Si, possess the excellent properties, The remnant polarization, coercive voltage, and leakage current density of the capacitor, measured at 5 V, are～25.1μC/cm2,～0.83 V, and～7×10-4 A/cm2, respectively. Moreover, the properties of Pt/SRO/PZT/SRO/Ni-Al/Cu/Ni-Al/SiO2/Si capacitor stack with Cu were evaluated when the temperature of samples were changed from room temperature to 100℃. It is found that the polarization, dielectric constant and the leakage current were only slightly changed instead of intrinsically dramatic change, which is attributed to leakage current, lattice vibration and thermal activation, respectively.The SRO/BFMO/SRO/Ni-Al/Cu/Ni-Al/SiO2/Si capacitor was investigated with BFMO as ferroelectric layer to achieve the integration of BFO with Cu interconnect. In SRO/BFMO/SRO/Ni-Al/Cu/Ni-Al/SiO2/Si stack capacitor, BFMO is well-crystallined and Cu is intact, and the ferroelectric hysteresis and small leakage current indicated the successful integration and its potential application of BFO with Cu in microelectric craft.Barrier performance of 10-nm-thick Ni-Al-N layer is investigated. It is found that the Ni-Al-N film keeps amorphous and no obvious reactions/interdiffusions are observed after high temperature annealing at temperatures up to 650℃, indicating that the amorphous Ni-Al-N layer has good barrier performance. Unlike the conventional failure mechanism of a barrier layer resulting from that Cu diffuses into SiO2/Si and reacts with Si to form copper silicides, agglomeration of Cu film in the Cu/Ni-Al-N/SiO2/Si heterostructure happens when the annealing temperature is higher than 700℃, which is attributed to the dewetting of Cu film with Ni-Al-N during high temperature annealing. Moreover, the activation energy is estimated to be 1.1 eV based on the Kissinger equation, which is two times than Cu/SiO2(0.6 eV), suggesting that inserting Ni-Al-N barrier can improve failure temperature and the stability of interconnect structure.