Research And Hardware Implementation Of H.265/HEVC CABAC Entropy Coding

In recent years,with the development of the Internet and communication technologies,people's demand for video has developed rapidly in both resolution quality and video usage,which puts higher requirements on the hardware implementation of video coding.The compression efficiency of the high efficiency video coding(HEVC)standard is 35?40% higher than that of H.264,but its complexity is also 2?4 times higher than that of H.264.HEVC retains the more complex contextbased adaptive binary arithmetic coding(CABAC)as the only entropy coding method,and the new prediction structure and coding method also makes the syntax element type increase and the coding rules more complicated during entropy coding.Therefore,the throughput of entropy coding has become one of the bottlenecks of video encoders.In this paper,the hardware framework of CABAC entropy coding is designed.On this basis,the modules of entropy coding are implemented and optimized,and the storage structures of reference data and residual coded data are designed.In the implementation of binary arithmetic encoder,this paper adopts four-way parallel architecture based on the single-channel four-stage pipeline structure.Aiming at the problem that the timing path is too long and the working frequency is too low in the parallel implementation in result from the data dependence of the arithmetic coding,this paper uses the incomplete dependence between the previous coding interval and current interval to split the critical path Range Updating into two stages in the pipeline.On the basis of this,the same method is used for the calculation of the renormalization and renormalization times of the coding interval.Such a structure can effectively shorten the timing path length.In the implementation of the residual coefficient coding module,the residual coding module is divided into coefficient group(CG)coding control module and CG internal syntax element coding module,and adopts a three-stage pipeline structure to improve the throughput of the residual coding.Based on the distribution characteristics and coding method of residual data,the disadvantages of traditional pipeline residual coding in throughput are analyzed.The traditional method will lead to clock waste when encoding the all-zero CG which lies after the last none-zero CG.Therefore,this paper proposes an implementation method based on CBF pre-calculation of CSBF to quickly skip all-zero CG before coding the last non-zero CG.According to the simulation results,the method can increase the throughput of 4.027% on average in P frame,and I frame can increase the throughput by 1.311% on average.The entropy coding module designed in this paper is simulated by simulation software,and the results are consistent with the HEVC reference software.Hardware verification on the Intel Arria 10 SOC development board also yields correct results.Integrated with the corresponding device library,it runs at 210.78 Mhz and supports1080 p HD video real-time encoding at 30 frames per second.