Build General FPGA Rapid Prototype Based On OR1200

Based on the research of variable frequency control chip, the paper is proposed system-level design scheme of OR1200-based SOC chip, aiming to shorten the SOC design cycle, reduce the prophase of design in an enterprise. This design complete the design of the SOC chip system architecture, design and verify the core module of the chip, on the other hand built the FPGA rapid prototype validate platform of the chip, completed a prototype of the chip validation and design optimization.First, the author introduces the development situation and advantages of the hardware and software collaborative verification technology, proposes design procesure which achieves transplanting from the SOC to Altera FPGA based on system prototype validate of FPGA in this foundation, and also introduces the architecture and Cyclone on-chip resources of Altera Cyclone II FPGA in detail. Then, puts forward the design for system architecture of the SOC chip, including:the OR1200 microprocessors, Wishbone bus design specifications and SOC chip chip resources, and also the SOC chip address allocation plan. Then, completed the main module's design work depending on the design requirements, namely Wishbone bus IP core and UART, and it IP core is simulated. Finally, based on FPGA prototype validate processes, built the SOC chip prototype system verification platform, completed the hardware design optimization and software design of the construction of the two aspects of the environment, and completed the SOC system basic FPGA prototype system verification on this basis. It shows that the system is designed to meet the design of SOC standard requirements through the simulation results.This subject mainly completes rapid prototyping platform based on FPGA design and implementation of the OR1200 microprocessor, to construct the core which including software and hardware platform for the embedded SOC system. Hardware system to open source 32-bit RISC nuclear and dry, mainly Wishbone bus simulation validated module to join them one by one OR1200 embedded systems. Then verification on FPGA. Software part includes cross-compiling environment establishment, the cross-compiling tools finally generating an executable program downloaded to memory. Finally in the Altera DE2 development board validation system could stable movement.This paper put forward the main contribution for the SOC chips based on the OR1200 design, completed the Wishbone bus IP module and UART IP module circuit module design; Built the chip FPGA rapid prototype validate platform; The author has solved the design involves many technical difficulties, such as:Wishbone bus and UART IP module RTL design; Chip FPGA transplantation; The OR1200 processor FPGA design optimization, etc.