Research And Implementation Of IC Designs Prototyping Technique

As the rapid expanding of ASIC design scale and complexity of the product ,time to market is becoming shorter and shorter, the time of verification is often occupy a large proportion throughout the design process. Existing EDA verification software could not reach to satisfying covering rate when deals with large scale designs or high rate data processing.The emergence of FPGA prototype greatly improved the efficiency of verification. FPGA prototyping method use FPGA device to implement the user's IC design under verification. In this way verification engineers can test the logic functions of the chip, and software engineers and systems engineers can do a variety of designs parallel on the FPGA prototype before the IC design signed out. This parallel ability to work further reduces the time from design to product, which provides a strong support to rapid market-oriented trend.Although the FPGA capacity is increasing, but many very large scale ASIC can not be implemented on one FPGA. It faces the situation of dividing one IC design into multiple FPGAs. Multi-FPGAs prototyping is widely used by IC designers. Different from the traditional single-FPGA verification, multi-FPGA verification introduced two typical problems, namely, the logical partition and pin limitation.How to divide logic designs, what kind of partition algorithm is used and what steps is followed, these are known as logical partition problem. The logic partition algorithm based module boundary will be helpful to logic partition. Constructing algorithm based on this method is also the trend to build software for an automated partition research. At the same time, when we partition different modules into different FPGAs, the interconnection between the two ASIC modules may be reached at 10000, while the FPGA available I/O number is limited. On this situation, how to use the advanced partition algorithm optimize the interconnection between the modules, how to multiple the physical interconnect lines, these two questions are the keys to FPGA simulation. This paper proposes a high-speed serial communication protocol, concluding the relationship between operating frequency of the system and the serial transmitter frequency which can be used as building IO multiplexing module. In this thesis, I designed serial communication module and constructed the structure of time-division IO multiplexing, allowing parallel data transmission on a physical interconnection line in an efficient way, improving the operating frequency of prototyping platform.