Design And Research Of The Bilateral MPEG-2_DS3 Adapter System

With the rapid development of computer science and internet technology, all kinds of information,such as news and video,is becoming more and more accessable.And it presents both opportunities and challenges to the field of digital television.Only taking full advantage of multimedia resource to meet the requirement of fatidious audience can digital television consolidate its existing markets. The key problem is to improve the capacity of Broadcasting and TV network.However,with the maturity of the SDH network,the transmission cost was considerably reduced in recent years. Transporting the MPEG-2 Transport Stream via the SDH network will be a practicable plan.Thus,the development of the DS3 network adapter system will have notable economic benefits.First of all, the paper introduces several related international standards and then provides a solution to convert MPEG-2 Transport Stream to DS3 frame.The implementation of all the function blocks is discussed in detail.The paper also analyses the cause for the problems and comes up with answes.This paper provides a solution to convert MPEG-2 Transport Stream to DS3 frame.The adapter system is bilateral,and it is able to convert DS3 frame to MPEG-2 Transport Stream which will be exported through ASI interface as well. PCR jitter is smoothed in the adapter system in order to guarantee that the decoder will work exactly. The adapter system is also capable of detecting and handling these faults which are caused by plugging in or plugging out the transmission line.In addition,sevel LED lights will indicat the current state of the adapter system,so that the user can easily figure out where the problem is.A novel approach for DS3 frame generating is present in this paper, which simplifies the generation procedure by pointing to every bit of a DS3 frame by only one counter.Moreover,this paper optimises the structure of the adapter system and combines two function blocks into one,so that it saves the FPGA hardware resources and promotes the system speed remarkably.This design adopts programmable logic device FPGA and realizes all the functions of the adapter system on xc5vsx50t chip of Virtex-5 series of Xilinx Company on the basis of Verilog HDL. The LIU chip DS3154 is used as the physical layer interface which is specified in the DS3 standard.The FPGA is the main controller in this system.It sets up the DS3154 before the adapter system will start to work and monitors the state while the system is running. The logic design is accomplished on the basis of ISE11.4 of Xilinx Company. The design completes the function simulation in ISim Simulator.The software tool "Chipscope" is used to observe the DS3 data and the bit stream analyzer is used to analyze the transport stream during the test.Finally,this paper proposes some test results of importance. It shows that the design is feasible.