The High Performance Fpga Mapping Algorithm Research Has Extensive Adaptability

The design of FPGA includes the construction of the FPGA chip and the building of the corresponding software system. There is a more adaptable mapping algorithm FDUMAP based on graph isomorphic algorithm in geography, by which PLBs with LUT, DFF, MUX and rapid carry-in chain can be processed. This is a great break through in the unity of the mapping algorithm. But the problem is that the complicity of this algorithm grows exponentially as the number of the component types increases. Besides, this algorithm shows worse performance comparing with the former one-to-one mapping algorithm.This article analyzes the common characteristics in the structure of the modern FPGA’s logic components, classifying similar components such as LUT, DFF, MUX, F5MUX, AND gate and XOR gate into one type. The new algorithm presented in this article can not only process PLBs with LUT, DFF, MUX and rapid carry-in components, but can also deal with F5MUX, AND gate, XOR gate and other components that are now widely used in modern FPGA structure for specified functions. That is to say, the new algorithm can be adapted in modern FPGA chip of arbitrary scales and component types. In order to reduce the complexity, this paper presents some new ideas such as layer of PLB structure and classification of PLB components. At the same time, a matching degree coefficient is introduced to improve the efficiency and performance for the algorithm.The results show that the result this tool generated equal to the special logic block mapping tools and even better than them .