And The Results Using The Duppack Packing Method

FPGA has become one of the most common way in the field of digit circuit. The quality of CAD tool by which maps user circuit to FPGA is an important factor in determining the performance of the FPGA. Packing is a critical step for the realization of the mapping from the user circuit to the FPGA hardware structure in CAD flow. It converts previous output netlist of gate level into a netlist by FPGA logic cells. With the increasing development of semiconductor process and as the market demand driven, programmable logic cell structure is more and more complex in the modern commercial FPGA and chip’s structure updates are frequent. Traditional packing tools based solely on a simple model of the academic, has been unable to meet demand, and need to make the corresponding changes for different chip structure.A Circuit Rewriting Instruction System is designed and a FPGA pack method Dup-Pack based on CSPack is presented. Only needs to change instruction flow description file, Dup-Pack can implement packing for different FPGA chip. It first replaces the Derivative Function Cell in user circuit netlist with Standard Function Cell, then packs the Standard Function Cell, so the number of sample circuits reduction is achieved with implement of the advanced logic function packing. Experiments show that Dup-Pack compared with T-VPack achieves11.26%reduction in chip area, and the speed of pack improves2.77times compared to the traditional CSPack when implements the same logic function packing. This paper proposes a bit-stream level simulation approach by function model of the FPGA chip. Functional model of FPGA configs its function according to the bit-stream file. Signal situation of any node inside the model can be observed during the process so the bit-stream file can be verified. Based on FDP2which is an independent research and development FPGA chip by Fudan University, the function model has been built and it can be used for the experiment of bit-stream level simulation. The method can be used to quickly find error and locate it during verifying the bit-stream file.