Broadband Phase-locked Loop, Used In High-speed Phy-hdmi Transmitter

A PLL in high speed PHY is described and analyzed in this thesis. Clock generators are important build-in blocks in many communication and high-speed digital systems. Their performance will influence the system performance directly.This thesis reviews the architecture of clock generators firstly. Then it describes the clock generator PLL which is in general application. After that, the small-signal, transient characteristics are analyzed and discussed.Since low noise is a key target in clock generator, a more detailed analysis about clock generators noise is given in the thesis. There are two metrics to evaluate the noise of clock signal. One is phase noise, and the other is timing jitter. The thesis clarifies some concepts about jitter. After that introduce the most important block ring VCO, its noise characteristics is analyzed. Finally review the noise influence of each block of PLL based on the transfer function is considered.In this design, the loop bandwidth, roll-off rate, damping factor and the phase noise are optimized properly. The original 1st order loop filter is rebuilt, and some optimized circuits are implemented. For example, equivalent transform the loop filter to save the extra charge pump and make the loop filter easy extend to be higher order loop filter; By feedback circuit it can reduce the current mismatch of charge pump effective. Because of the basic feature of self-bias PLL, the ratio of loop bandwidth and reference clock can be kept to be a certain range so that both of the lock time and input tracking jitter can be improved.