| In order to meet the growing data transmission needs of people,high-speed serial communication(SerDes)has received wide attention due to its low cost and strong anti-interference ability.The spread-spectrum clock generator(SSCG)is an important module in SerDes,and its jitter is critical to the system's bit error rate(BER),especially with the additional jitter of spread-spectrum technology that effectively suppresses electromagnetic interference(EMI).Realizing SSCG with high stability,high reliability,low power consumption,and low jitter is one of the problems to be solved in high-speed SerDes.This thesis first introduces the theoretical basis of the SSCG.Interpretations and mathematical expressions of common parameters in SerDes are given in the loop analysis.For the sub-modules of the SSCG,the noise analysis method and the reduction method,and the system linearity compensation scheme are proposed respectively.In addition,the thesis also deduces the mapping relationship between phase noise,reference spurs and other indicators commonly found in wireless RF system and random jitter and deterministic jitter in wired communication.Finally,the key technical solutions for the three problems to be solved in the SSCG are proposed,including high-reliability spread-spectrum modulation technology,highly compatible frequency expansion technology,and temperature adaptive technology of voltage-controlled oscillator.In order to verify the feasibility of the technical solution,this project implements all circuit design and layout design under the PCIe-Gen4.0 physical layer protocol.Under the GF FD-SOI 22 nm process,the SSCG designed in this paper can effectively achieve 18.6dB spectral tone reduction and 0.75% modulation depth at 8GHz output,effectively reducing random jitter and deterministic jitter to 286 fS and 278 fS,and core power consumption as low as 8.98 mW.The output duty cycle is 50±0.1% and the bandwidth can cover 1.18-8.95 MHz. |
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