Research Of 32K-16MHz Full-integrated CMOS Low Power High Accuracy Clock Generator

A low-frequency sleep clock(such as 32KHz)and a high-frequency operating clock(such as 16 MHz or higher)are often both required in SoC.A stable and reliable clock is very important for the SoC.The accuracy of the clock generator often determines the performance of the entire system.At the same time,it is necessary to consider both power consumption and area specifications.In this paper,the advantages of RC relaxation oscillator and ring oscillator are combined through PLL(phase-locked loop)technology to improve the overall energy efficiency.An RC relaxation oscillator is used to generate a 32 KHz clock with good frequency characteristics,and then this clock signal is used as an input reference signal of PLL frequency synthesizer with a ring oscillator in the loop to achieve a low-power,high-precision 16 MHz clock.The capacitance area of the conventional RC relaxation oscillator is relatively large.The RC relaxation oscillator in this paper adopts a multi-vibrator structure.The negative-voltage charging structure reduces the capacitance area by about half compared with the conventional structure.In addition,the long-term stability of the multi-vibrator is better,which is beneficial to improve the real-time response capability of the system.When the input reference frequency of the PLL is low,the area of the loop filter capacitor in the traditional charge pump PLL is large,which is not conducive to integration.This article adopts a DPLL(digital PLL)scheme.The digital filter in the loop is composed of a PI(Proportional Integral)controller,so that the chip area of the PLL can be greatly reduced.The coefficient of the proportional integral controller is optimized to improve the PVT(Process Voltage Temperature)performance of the system.Particularly,this paper proposes an innovative non-constant-resolution Fibonacci coefficient TDC(Time Digital Converter)structure and binary output mode.The number of D-flip-flops and delay units is greatly reduced under the same loop lock time Compared with the traditional constant-resolution structure.The number of time units is greatly reduced,which reduces the power consumption and area of the circuit.This paper analyzes the Z-domain model of the DPLL in detail,and fulfill the system modeling and loop parameter design of DPLL based on Simulink.Finally,the transistor-level circuit design was completed based on the 0.18 um CMOS process.Simulation results show that when the input reference frequency is 32 KHz and the output frequency is 16 MHz,the power consumption of the DPLL is about 190 u W@2.4V,the eye diagram jitter is about 46 ps,and the estimated chip area is only about 0.03mm2.A complete system simulation of the first-stage RC relaxation oscillator and DPLL,the eye diagram jitter is about 56 ps @ 16 MHz.