Research And Design Of Clock Generator In Rfic For Satellite Navigation System

Global Navigation Satellite Systems (GNSS) has been widely used in a variety of civilian applications, which provides the fundamental physical quantities of the absolute position, velocity, and time information to users. Up to now, the United States Global Positioning System (GPS) is the only fully operational GNSS. The European Union's Galileo positioning system is a GNSS in initial deployment phase, scheduled to be available in 2013. China's Compass II will be expanded into GNSS by 2015. As the current applications only use one of these GNSS signals, they have poor and unstable sensitivity performance under some situation, especially for multipath interference and jamming. It is significant to have two signal channels for simultaneous reception of GPS, Galileo, and Compass to over-come these limits.Based on the analysis of different structures of wireless receivers system, this work combined with laboratory's low-power multi-mode multi-band GNSS receiver project proposed a new analog and baseband clock sampling structure. In this structure the clock generator based on ring oscillator directly provides clock signals to the autoatic gain control loop and analog-to-digital converter as well as digital baseband. Compared to other traditional architectures, this ring oscillator based clock generator provides a more flexible clock frequency and consumes less power.The main contribution of this work is the design of a low-noise 62MHz clock generator based on the analog and baseband clock sampling structure and using 180nm CMOS. The clock generator directly provides clock signals to the automatic gain control loop and analog-to-digital converter as well as digital baseband of the multi-mode multi-band global positioning receiver system. The ring oscillator consists of four Current control delay cells with Current-Steering Amplifier (CSA) circuit. These fully switching differential delay cells are employed to reduce the phase noise of the ring oscillator. For the low noise structure, the total phase noise of the clock generator is about -113.5dBc/Hz at 1MHz offset frequency. The ring oscillator exhibits a wide tuning range from 62MHz to 316MHz. The clock generator takes up layout area of only 280×300μm2, while consuming 1.6mW with a bidirectional buffer.