Research On Ring Oscillator-based Robust CMOS High-speed Clock Circuit

CMOS ring oscillators have been a popular candidate in numerous integrated circuits for their low power consumption,wide tuning range,small silicon area,and reconfigurability as other clock generators.However,its phase noise performance and reliability issue are the lim-itations of its further usage.This thesis considers the requirements of some specific applica-tions,e.g.,GHz-range RF transceiver,and does multi-layer research on CMOS ring oscillator and its related clock generation circuits.This research integrates reliability theories,circuits design techniques,and system architectures.Based on this topic,the reliability analysis and de-sign of three different clock generation circuits are performed,including a ring-oscillator-based frequency divider,an eight-phase non-overlapping clock generator,and a digitally-controlled oscillator.The circuits,as mentioned above,are all fabricated in standard CMOS technologies and verified through measurements.The main contributions and innovation are as follows.Since the current start-up analysis cannot provide accurate predictions on oscillation and helpful directions on optimization simultaneously,this thesis proposed a novel reliability-oriented start-up analysis of ring-oscillator-based injection-locked frequency divider.According to the proposed analysis,the improved design achieves a good trade-off between the locking range and reliability.Monte Carlo simulations confirm that the improved injection-locked frequency divider can eliminate the start-up problem of the conventional design.The improved circuit is designed in a standard 0.18?m CMOS technology and provides orthogonal four-phase outputs.It can start up reliably under different supply voltages and the whole industrial temperature range.It achieves a locking range of 147%and only consumes 0.25 mW.This thesis presents a duty-cycle imbalance correction circuit for the ring-oscillator-based eight-phase non-overlapping clock generator to alleviate the harmonic foldback when it is used in a mixer-first receiver.By inserting a pseudo-multiplexer between every two cells,the correc-tion circuit could suppress the duty-cycle imbalance in the eight-phase clocks while maintaining GHz-range output frequency.The Monte-Carlo simulation shows the proposed correction cir-cuits can remove the undesired imbalance and work under various process deviations.This clock generator is designed and fabricated in a standard 0.13?m CMOS technology and can work at the highest frequency of 2.5 GHz while consumes 2.4 mW under a 1.2 V supply voltage.A digitally-controlled oscillator for a multi-band digital array radar system is also proposed with small-area,wide tuning range,high linearity,and high reliability.Thanks to its negative feedback architecture,this oscillator is insensitive to Process-Voltage-Temperature variation.A novel linearity enhancement technique is also proposed.A one-point calibration method based on the resistor array is chosen and designed in a standard 55 nm CMOS technology.The digitally-controlled oscillator can work from 1.3 GHz to 2.5 GHz,with a tuning range of64%and a silicon area of 0.04 mm~2.It also achieves high linearity,with an INL of 4.64 LSB.Compared with the conventional design,it is reduced to 43%.