Efficient Fpga Implementation Of Broadband Digital Channel Surveillance Receivers

Digital channelized receiver, which has the advantages of broadband instantaneous frequency coverage, high sensitivity, large dynamic range and simultaneous signal detection ability, is the main research subjects of the radar intercept receiver. In digital channelized reconnaissance receiver system, signal detection and digital channelized are the two key technologies in signal pre-processing which spans from intermediate frequency signal output to baseband. The former affects the quality of system-wide surveillance to a great extent. The results of parameter estimation and signal sorting are directly affected by the measuring precision of the time of arrival (TOA) and pulse width (PW). The latter, which is the core part of the wideband digital channelized receiver, separates the intercepted signals by frequency-domain and shifts them to baseband after non-aliasing decimation in order to reduce the chip's speed requirements in the subsequent signal processing. It is the starting point of this dissertation. Supported by two corresponding programs, two key technologies, signal detection and channelized in digital channelized reconnaissance receiver are studied. The implementation on field programmable gate array (FPGA) of the whole system is also studied.The main contributions of the dissertation are summarized as follows:1. The non-cooperation signal detection theory is discussed firstly. Then some pulse signal detection methods which can be implemented in hardware are analysed. An autocorrelation algorithm for real-time detection of radar pulses is proposed in this dissertation. Compared with the original algorithm, the proposed one improves the accuracy of TOA and PW for narrowband pulse estimation, possesses the ability of detection and estimation for wideband pulse. Also, it can be easily implemented in hardware. The simulations show it has good detection performance in real-time processing environment.2. The theoretical foundation of the digital channelized, the multi-rate signal processing technology is discussed. Based on this theory, the digital channelized architectures with polyphase filter banks are deduced, designed and simulated in accordance with the target requirements. Then the digital channelized receiver is implemented on FPGA by parallel processing equivalent structure. The simulation and testing results are also presented.3. A wideband digital channelized reconnaissance receiver system which applies the wideband digital channelized reconnaissance technique is presented. The hardware platform is introduced and the system function specifications are completed. The flow of the channlized parameter estimation channel is explained briefly. The design and implementation of digital channelized receiver on FPGA are completed. The reconnaissance receiver performance testings are also completed to verify the effectiveness of the system work.