Algorithm Research Of Efficient Digital Channelized Receiver Based On Single-Rate Filter Bank Technology And Its FPGA Implementation

Digital channelized receiver has the characteristics of large instantaneous bandwidth, good frequency selectivity, large dynamic range and plays an important role in modern electronic warfare(EW). In order to improve the issue that the digital channelized receiver based on polyphase filter bank has the shortcoming of high complexity and its adjacent channels can’t be combined to form a wider sub-channel, this paper focuses on the algorithm research and the implementation on FPGA platform of the single-rate digital channelized receiver. The main work of this paper includes:it researches the algorithm of the Fast Filter Bank and the algorithm associated with it. Based on the PXle modular virtual instrument, it implements the core module of the digital channelized receiver and other functional modules that related to it.Besides,it also designs the human-computer interaction interface and tested the whole system.Firstly,the paper introduces the background and the significance of the research on digital channelized technology.By analyzing the current research, we recognized that domestic research on digital channel of technology is still insufficient,therefore it’s necessary to study on the digital channelized technology.Secondly, this paper introduces the overall architecture of the modern digital channelized receiver, analyses the FFT-based channelized architecture and its shortcomings and proposes two methods that can compensate poor FFT filtering performance.Firstly,the channelized architecture based on the polyphase filter bank can design the wanted filter bank parameters flexibly,but it has to consume more multipliers. Secondly, the channelized architecture based on the single-rate fast filter bank can not only compensate for the poor performance of the FFT prototype subfilter and design the high performance filter bank, but also design the subfilter coefficients based on FRM technique and its complexity compared to FFT roughly equal.This section studies the derivation of the FFB algorithm, the design method of the subfilter coefficients based on the FRM technique and the node-modulated FFB as the improved scheme of the FFB. Then a comparison is made between FFT, polyphase filter bank and FFB in the filtering performance, the number of multipliers consume and the application scenarios. Finally,the paper studies the channelized subsequent processing algorithms such as extraction algorithm and detection algorithm for the output data of subfilters.Thirdly, based on the PXIe modular virtual instrument, the 64 channels digital channelized receiver system has 50MHz analysis bandwidth is implemented on the Labview FPGA platform. The paper expounds the design of the modules and the detailed implementation process of the modules. The modules includes the digital channelized core module,the digital channelized subsequent processing module,the high-speed data transmission module,the RF signal record module and the RF signal playback module. Digital Channelized core module is the core of the whole system and realizes channelized filter of the digitalized signal. Digital Channel subsequent processing module includes the sub-sampling module and the channel detection module, the function of them is the deceleration processing and effective data detection of the subchannels’ data. High-speed data transmission module is for high-speed information exchange between FPGA and HOST and reliable real-time transmission.RF signal record module is for data recording and RF signal playback module is for the playback of the recording data to analyze indoor.Finally,The paper introduces the building process of the hardware instrument including vector signal analyzer and vector signal generator’s building.Then the entire digital channelized receiver system is tested on the Labview FPGA platform and the test results were analyzed and compared with the theoretical results to verify the correctness of the system.