Sigma-delta Modulator Research And Design

Traditional data converters, in order to prevent aliasing noise, requires high-performance pre-filter. However, high-precision analog components are affected by integration, temperature and other factors. Therefore, ADC, it is necessary to improve analog filters, which is difficult. To solve these problems, Sigma-Delta modulation is applied to the data converter. Sigma-Delta modulation makes use of over-sampling and noise shaping technologies, the requirements of the internal devices of Sigma-Delta Conversion are not that high like conventional converters. Therefore, Sigma-Delta modulation ADC compared to the traditional ones has high resolution, good stability, and good linearity. Sigma-Delta ADC is easy integrated with digital circuit, suitable for handling high-resolution audio signals and data acquisition.In this paper, Sigma-Delta modulation techniques are studied and analyzed and a 12-bit second-order Sigma-Delta Modulator for Civil audio system application is designed. This thesis uses MATLAB, SIMULINK software for Sigma-Delta modulator behavioral simulation and analysis of non-ideal factors. Analysis of non-ideal factors include: Non-linear integrators, op-amp DC gain non-ideal clock jitter tolerance, capacitance and noise. The power density spectrum analysis of Non-ideal Sigma-Delta Modulator simulation results show that: non-ideal op-amp DC gain and the integral circuit nonlinear factors impact on the output signal to generate harmonic noise, background noise. In this paper, single-loop second-order modulator structure and a 1-bit quantizer are chosen. Spectrum analysis showed that the non-ideal factors influence mainly on the first stage output of the circuit. Design and simulation of of various modulator circuit modules are by Cadence's EDA software, including operational amplifier, comparator, etc. op-amp is folded cascode (folded-cascode) structured. Simulation results show that op amp DC gain is 92.13dB, unity gain bandwidth of 115MHz, phase margin 65.66°, meeting the design requirements. In this paper, circuits are designed by 0.5um CMOS PDK and the test results meet the specification.