Design Of Sigma-delta Modulator For Audio System

Sigma-Delta Analog to Digital Converter (ADC) can achieve high converting resolution, using oversampling, noise-shaping and digital filtering technique. It can be implemented with the mature CMOS digital Integrated Circuit technology and can obtain very high resolution with relative simple circuit architecture, so it has been widely used in high quality digital audio application.Sigma-Delta ADC consists of an analog Sigma-Delta modulator and a digital decimation filter. The design of a Sigma-Delta modulator that can be applied to digital audio signal system is presented in this dissertation. Firstly, we analyze the principle of the modulator, compares the advantages and disadvantages of different modulator architectures. The selection of the design parameters, including the order of the modulator, the oversampling rate and the bit of the quantizer is completed. The second-order 1-bit single-loop architecture with the oversampling rate of 256 times is adopted in this thesis, which satisfies the design requirement of the resolution of 16 bits. Secondly, the behavioral model of the selected modulator architecture is simulated by MATLAB. Under ideality conditions, the signal to noise rate (SNR) can achieve 102dB within the audio signal bandwidth of 20 KHz, satisfying the design requirement of 16 bit resolution. Analysis of the non-idealities of the modulator is also presented. Lastly, the modulator circuit, including switched capacitor integrator, fully differential folded-cascode operational amplifier, comparator and two-phase non-overlapped clock is designed, and the circuit simulation is finished by CADENCE SPECTRE.In this dissertation a Sigma-Delta modulator with the resolution of 16 bits is designed, which is aimed at the audio input signal of 20KHz. The modulator adopts a fully differential switched-capacitor circuit. The capacitor is implemented by MIM structure. The modulator is implemented in UMC 0.18μm mixed-signal technology with a supply voltage of 1.8V, the power dissipation is about 6.5mW. The simulation results illustrate that, with an oversampling rate of 256 and a sampling frequency of 10.24MHz, the signal-to-noise-ratio (SNR) and dynamic range (DR) of the modulator can reach 97dB and 103dB respectively, which satisfies the 16 bits resolution. The chip area of the modulator is 0.209 mm~2.