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.16-bit Sigma-delta Adc Design And Energy Meter

Posted on:2006-07-23Degree:MasterType:Thesis
Country:ChinaCandidate:P WuFull Text:PDF
GTID:2208360152490764Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
With the popularization of the ammeters, the power energy metering IC have been used widely. In the power energy metering chip , there are analog to digital converters to process the voltage signals of the current censor and the voltage sensor. Because the analog to digital converter which used sigma-delta modulation architecture has no strict requirements of matching characteristics , this ADC is independent of the external environment and can be integrated easily, so comparing other types ADC , it is more suitable for the power energy metering chip.The aim of this essay is to design a two order sigma-delta modulation which will be used in the power energy metering chip, its sample frequency is 900 Khz, and the signal bandwidth is 14khz. At first , the article introduce the present and the future situation of the sigma-delta modulation in china and abroad, then analyze the architecture and the work principals of the power energy metering chip, and introduce the basic theory of the sigma-delta modulation. Then, analyze the problems which need to be resolved in the design, mainly lies in the improvements of the performance of integrator and reduce the circuit noise. At last, this paper discusses the realization of all the specific modules in particular, mainly lies in the choice and design of integrator, operational amplifier, and comparator, then the module and the top level simulation results are given.
Keywords/Search Tags:sigma-delta modulation, signal-to-noise ration, oversample, switch-capacitance circuits, folded-cascode
PDF Full Text Request
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