Study And Design Of Sigma-Delta Modulator For VoIP

The analog-to-digital converters (ADCs) are widely used in video, audio, communication, seismic exploration and medical electronics systems as the interface circuits. With the increasing processing capability and speed of these systems, the accuracy and speed of ADCs need to be improved correspondingly.The oversampling Sigma-Delta ADC, which is different from traditional ADCs, adopts two key technologies of oversampling and noise-shaping to drive most quantization noises out of the signal band frequency. The out-of-band quantization noises can then be removed by using the digital low-pass filter, resulting in a significant increase in conversion accuracy and making it very suitable to be applied in the audio and digital phone fields.Based on a real engineering project, in-depth investigations on the modulator of a high resolution Sigma-Delta ADC for VoIP chip were performed in this work. A chopper-stabilized Sigma-Delta modulator with a second-order single-loop structure was successfully designed and implemented using switched-capacitor circuits. The modulator has an oversampling rate of 128 and a signal bandwidth of 24 KHz, The quantizer uses single-bit internal quantization. The working principle of Sigma-Delta modulator, the structure characteristics of the single-loop, cascade and multi-bit quantization modulators were firstly discussed. Meanwhile, effects of various nonidealities in real circuits on the modulator performance were also analyzed in detail. These nonidealities include the finite direct-current gain, the finite unity-gain bandwidth and the slew rate of the operational amplifier, the circuit noise and the clock jitter. Then, the behavior simulation was performed on a 2nd-order Sigma-Delta modulator under Matlab. Circuit-level specifications were determined for circuit design., Furthermore, designs of various unit circuits in the Sigma-Delta modulator, including the switch-capacitor integrator, the comparator, the single-bit DAC and the non-overlapped clock signal generator, were completed at the transistor-level. Finally, the simulation verification of the whole circuit was realized by using Cadence Spectre.A CSMC 0.5μm CMOS process was used in this work. Simulation results indicate that, at a power supply of 5 V and a sampling frequency of 6.144 MHz, the designed Sigma-Delta modulater has a dynamic range of 81.6 dB and a convertion resolution of 13.26 bits, meeting the expected design requirements.