Research And Design Of Sigma Delta Modulator For Electric Energy Meter IC

With the development of social, high precision, low-power and network function Electronic Energy Meter has been widely used. In Electronic Energy Meter, the metering IC is much important. Actually, Energy Metering IC use sigma-delta ADC as analog to digital converter. Sigma-delta ADC using oversampling techniques and noise shaping technology, and effective inhibition of the signal-band quantization noise and improve the SNR.Compared to the traditional Nyquist converts, Sigma-delta ADC lessen the requirements of analog circuits, simplify the design of analog circuit and reduce the cost of manufacturing. In this paper, a sigma-delta modulator is designed for an energy metering IC. It use 256 times over-sampling rate, signal bandwidth is 2K, with 14 bits precision. This thesis first analyzes the performance and characteristics of a variety of ADCs, after comparing each kind of structures, a Sigma-delta ADC is chose. Based on the analysis of the Sigma-delta modulator, this paper compares the traditional feedback feed-forward modulator in front of the performance and characteristics of the structures. Based on the results of comparative analysis, this paper chose the more advanced mode of second-order feed-forward modulator structure, which is based on loop filter technique. With the traditional feedback structure compared to the feed-forward structure has the following advantages: First, the signal transfer function STF(z)=1,therefore, the harmonic distortion due to no-idealities in the modulator's loop filter can be significantly reduced. Second, feed-forward modulator can reduce the modulator's internal node signal swing, it making the system more stable. In this thesis, the behavioral of the modulator is simulated by MATLAB SIMULINK, then complete system level design.In the circuit-level design process, this paper divides the modulator circuit into following parts according to its function: sampling circuit, operational amplifier, comparator, two-phase non-overlapping clock circuit and bandgap circuit. Each module is designed with the requirements of the system. Based on CSMC 0.5μm /5V Si CMOS technology, using HSPICE the circuit-level design is completed. The simulation results show that the Op-Amp with open-loop gain 84.7dB, the phase margin is 67°, with a bandwidth of 44.8MHz; The comparator can distinguish 0.2mV at 100MH, power consumption is only 1.12mW; Reference output with a benchmark of about 2.5V, the smallest temperature coefficient of up to 52ppm /℃. Finally, this thesis uses HSPICE to carry on top-circuit simulation, the results show that this modulator with SNR 87.6 dB, reaching 14 accuracy requirements. Through the chip tests, the results show that the modulator circuit has been designed to meet the requirements of a certain practical value.