The. Sata2.0 Plus Decryption Interface Chip Control Module Design And Implementation

With the advent of the information age, the hard disk is becoming the main media for information storage. Its interface has developed from traditional PATA(Parallel ATA) to today's SATA(Serial ATA). Compared to PATA, SATA has some obvious advantages such as hot plug, fast transfer rate and higher efficiency in the implementation. SATA2.0 is the second generation of SATA standard, which allows an external hard drive transfer rate of the theoretical value increased from the first generation of 1.5Gbps to 3Gbps. In addition, SATA hard drive also has less and thinner cables, low power consumption and it is backward compatible with PATA. Now most of the hard disks in the market are based on SATA2.0 interface standards.If the hard drive containing confidential information is lost or stolen premeditated, the losses of the country or the company are inestimable. Now there is no domestic independent intellectual property rights SATA chip, so SATA2.0 interface encryption and decryption controller chip, whether for national security or commercial interests, has high research value and application value.This paper first analyses the SATA2.0 protocol simply, including the physical layer, link layer, transport layer and the command layer, and introduces the part which is very important to our future design in detail. Based on digital circuit design it gives the system architecture and design ideas. The whole system is divided into the physical layer interface unit module (PIU), the send control module (SCM), the receive estimate module (RE), the data process module (DPM), send interface engine module(SIE) and encryption and decryption chip interface module (ENCP). Then, it discusses how the SCM, which is the control logic of the system and the ENCP module of the data path are designed and implemented. After that it also gives the simulation results of each module. Finally, it introduces the scenario and the results of verification and test briefly. The design is implemented in Virtex 5 XC5VLX50T FPGA of Xinlinx. The test shows it has reached the requirements of the project. It is inserted between the hard disk and the host successfully which can encrypt and decrypt real-time data when it is transmitting. It has less effect on the efficiency of the write and read of the hard disk. It can communicate with encryption and decryption engine and supports configurable keys. The paper has a theoretical value and reference value about SATA2.0 interface encryption and decryption controller chip.