Encryption And Decryption Based On The Hard Drive Of The Sata 2.0 Interface Controller Chip Design And Realization

Serial ATA 2.0 is a high-speed serial link, which speed can reach up to 3Gbps. The serial link is a high-speed NRZ serial stream at specified voltage levels that utilizes Gigabit technology and 8b/10b encoding, at the same time it can support some technology characters, such as NCQ, port multiplier, interleaving start-up, hot swap and so on. The bus makes data transfer faster and more stable and reliable, so it is widely used in the storage areas, especially in the area of hard disk.With the advent of the information era, the need for data storage and data protection has been becoming more and more urgent. The encryption technique based on hardware has features of higher speed and reliable way of secret key encryption, so it gradually becomes the trend of data encryption. Integrating hard disk encryption and SATA2.0 interface circuit design and realizing hard disk encryption controller hardware have very important use value and research value.In the first place, this dissertation introduces SATA 2.0 protocol and ATA/ATAPI-6 command set, which include physical layer, link layer, transport layer and command layer analyze, four different categories of transport specification and commands in common use, put forward where need be paid attention to and where need be amended for protocol in the design process. And than, this dissertation describe system design of SATA 2.0 encrypt and decrypt controller chip, include apply environment, design specification and module partition, explain difficulty and the way to resolve and chip design diagram. Finally discuss the detailed realize of every modules.Assistant verification IP of the chip uses the SATA VIP of SYNOPSYS company, and use the Xilinx V5 FPGA as the ultimate realization flat, and in the end of this dissertation, explain the system verification and testing environment, as well as the results. From the test results we can get out the important function unit of this chip, such as receive estimate module, sent control module, data process module and send interface engine can work exactly, can process data transmission.The chip design methods discussed in this dissertation has been achieved in the SATA2.0 encryption chip control projects. It works normally on Xilinx V5 FPGA, has good performance and reaches performance requirements. The research fruit of SATA encrypt and decrypt control chip design and realize based on this dissertation is of some theoretic and economical value and can be applied to many purposes.